tlb.cc (8570:ea93f18eead8) | tlb.cc (8573:be51bef13962) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 338 unchanged lines hidden (view full) --- 347 EvenOdd = 0; 348 } else { 349 // Check odd bits 350 Valid = pte->V1; 351 EvenOdd = 1; 352 } 353 354 if (Valid == false) { | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 338 unchanged lines hidden (view full) --- 347 EvenOdd = 0; 348 } else { 349 // Check odd bits 350 Valid = pte->V1; 351 EvenOdd = 1; 352 } 353 354 if (Valid == false) { |
355 return new ItbInvalidFault(Asid, vaddr, vpn); | 355 return new InvalidFault(Asid, vaddr, vpn, false); |
356 } else { 357 // Ok, this is really a match, set paddr 358 Addr PAddr; 359 if (EvenOdd == 0) { 360 PAddr = pte->PFN0; 361 } else { 362 PAddr = pte->PFN1; 363 } 364 PAddr >>= (pte->AddrShiftAmount - 12); 365 PAddr <<= pte->AddrShiftAmount; 366 PAddr |= (vaddr & pte->OffsetMask); 367 req->setPaddr(PAddr); 368 } 369 } else { 370 // Didn't find any match, return a TLB Refill Exception | 356 } else { 357 // Ok, this is really a match, set paddr 358 Addr PAddr; 359 if (EvenOdd == 0) { 360 PAddr = pte->PFN0; 361 } else { 362 PAddr = pte->PFN1; 363 } 364 PAddr >>= (pte->AddrShiftAmount - 12); 365 PAddr <<= pte->AddrShiftAmount; 366 PAddr |= (vaddr & pte->OffsetMask); 367 req->setPaddr(PAddr); 368 } 369 } else { 370 // Didn't find any match, return a TLB Refill Exception |
371 return new ItbRefillFault(Asid, vaddr, vpn); | 371 return new RefillFault(Asid, vaddr, vpn, false); |
372 } 373 } 374 return checkCacheability(req); 375#endif 376} 377 378Fault 379TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) --- 62 unchanged lines hidden (view full) --- 442 } else { 443 // Check odd bits 444 Valid = pte->V1; 445 Dirty = pte->D1; 446 EvenOdd = 1; 447 } 448 449 if (Valid == false) { | 372 } 373 } 374 return checkCacheability(req); 375#endif 376} 377 378Fault 379TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) --- 62 unchanged lines hidden (view full) --- 442 } else { 443 // Check odd bits 444 Valid = pte->V1; 445 Dirty = pte->D1; 446 EvenOdd = 1; 447 } 448 449 if (Valid == false) { |
450 return new DtbInvalidFault(Asid, vaddr, VPN); | 450 return new InvalidFault(Asid, vaddr, VPN, true); |
451 } else { 452 // Ok, this is really a match, set paddr 453 if (!Dirty) { 454 return new TLBModifiedFault(Asid, vaddr, VPN); 455 } 456 Addr PAddr; 457 if (EvenOdd == 0) { 458 PAddr = pte->PFN0; 459 } else { 460 PAddr = pte->PFN1; 461 } 462 PAddr >>= (pte->AddrShiftAmount - 12); 463 PAddr <<= pte->AddrShiftAmount; 464 PAddr |= (vaddr & pte->OffsetMask); 465 req->setPaddr(PAddr); 466 } 467 } else { 468 // Didn't find any match, return a TLB Refill Exception | 451 } else { 452 // Ok, this is really a match, set paddr 453 if (!Dirty) { 454 return new TLBModifiedFault(Asid, vaddr, VPN); 455 } 456 Addr PAddr; 457 if (EvenOdd == 0) { 458 PAddr = pte->PFN0; 459 } else { 460 PAddr = pte->PFN1; 461 } 462 PAddr >>= (pte->AddrShiftAmount - 12); 463 PAddr <<= pte->AddrShiftAmount; 464 PAddr |= (vaddr & pte->OffsetMask); 465 req->setPaddr(PAddr); 466 } 467 } else { 468 // Didn't find any match, return a TLB Refill Exception |
469 return new DtbRefillFault(Asid, vaddr, VPN); | 469 return new RefillFault(Asid, vaddr, VPN, true); |
470 } 471 } 472 return checkCacheability(req); 473#endif 474} 475 476Fault 477TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) --- 32 unchanged lines hidden --- | 470 } 471 } 472 return checkCacheability(req); 473#endif 474} 475 476Fault 477TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) --- 32 unchanged lines hidden --- |