tlb.cc (8232:b28d06a175be) tlb.cc (8567:d154cd83c353)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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308
309 bool misaligned = (req->getSize() - 1) & vaddr;
310
311 if (IsKSeg0(vaddr)) {
312 // Address will not be translated through TLB, set response, and go!
313 req->setPaddr(KSeg02Phys(vaddr));
314 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
315 misaligned) {
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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308
309 bool misaligned = (req->getSize() - 1) & vaddr;
310
311 if (IsKSeg0(vaddr)) {
312 // Address will not be translated through TLB, set response, and go!
313 req->setPaddr(KSeg02Phys(vaddr));
314 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
315 misaligned) {
316 AddressErrorFault *Flt = new AddressErrorFault();
317 /* BadVAddr must be set */
318 Flt->badVAddr = vaddr;
319 return Flt;
316 return new AddressErrorFault(vaddr);
320 }
321 } else if(IsKSeg1(vaddr)) {
322 // Address will not be translated through TLB, set response, and go!
323 req->setPaddr(KSeg02Phys(vaddr));
324 } else {
325 /*
326 * This is an optimization - smallPages is updated every time a TLB
327 * operation is performed. That way, we don't need to look at
328 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
329 */
330 Addr VPN;
331 if (smallPages == 1) {
332 VPN = (vaddr >> 11);
333 } else {
334 VPN = ((vaddr >> 11) & 0xFFFFFFFC);
335 }
336 uint8_t Asid = req->getAsid();
337 if (misaligned) {
338 // Unaligned address!
317 }
318 } else if(IsKSeg1(vaddr)) {
319 // Address will not be translated through TLB, set response, and go!
320 req->setPaddr(KSeg02Phys(vaddr));
321 } else {
322 /*
323 * This is an optimization - smallPages is updated every time a TLB
324 * operation is performed. That way, we don't need to look at
325 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
326 */
327 Addr VPN;
328 if (smallPages == 1) {
329 VPN = (vaddr >> 11);
330 } else {
331 VPN = ((vaddr >> 11) & 0xFFFFFFFC);
332 }
333 uint8_t Asid = req->getAsid();
334 if (misaligned) {
335 // Unaligned address!
339 AddressErrorFault *Flt = new AddressErrorFault();
340 /* BadVAddr must be set */
341 Flt->badVAddr = vaddr;
342 return Flt;
336 return new AddressErrorFault(vaddr);
343 }
344 PTE *pte = lookup(VPN,Asid);
345 if (pte != NULL) {
346 // Ok, found something
347 /* Check for valid bits */
348 int EvenOdd;
349 bool Valid;
350 if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) {
351 // Check even bits
352 Valid = pte->V0;
353 EvenOdd = 0;
354 } else {
355 // Check odd bits
356 Valid = pte->V1;
357 EvenOdd = 1;
358 }
359
360 if (Valid == false) {
337 }
338 PTE *pte = lookup(VPN,Asid);
339 if (pte != NULL) {
340 // Ok, found something
341 /* Check for valid bits */
342 int EvenOdd;
343 bool Valid;
344 if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) {
345 // Check even bits
346 Valid = pte->V0;
347 EvenOdd = 0;
348 } else {
349 // Check odd bits
350 Valid = pte->V1;
351 EvenOdd = 1;
352 }
353
354 if (Valid == false) {
361 //Invalid entry
362 ItbInvalidFault *Flt = new ItbInvalidFault();
363 /* EntryHi VPN, ASID fields must be set */
364 Flt->entryHiAsid = Asid;
365 Flt->entryHiVPN2 = (VPN >> 2);
366 Flt->entryHiVPN2X = (VPN & 0x3);
367
368 /* BadVAddr must be set */
369 Flt->badVAddr = vaddr;
370
371 /* Context must be set */
372 Flt->contextBadVPN2 = (VPN >> 2);
373 return Flt;
355 return new ItbInvalidFault(Asid, vaddr, vpn);
374 } else {
375 // Ok, this is really a match, set paddr
376 Addr PAddr;
377 if (EvenOdd == 0) {
378 PAddr = pte->PFN0;
379 } else {
380 PAddr = pte->PFN1;
381 }
382 PAddr >>= (pte->AddrShiftAmount - 12);
383 PAddr <<= pte->AddrShiftAmount;
384 PAddr |= (vaddr & pte->OffsetMask);
385 req->setPaddr(PAddr);
386 }
387 } else {
388 // Didn't find any match, return a TLB Refill Exception
356 } else {
357 // Ok, this is really a match, set paddr
358 Addr PAddr;
359 if (EvenOdd == 0) {
360 PAddr = pte->PFN0;
361 } else {
362 PAddr = pte->PFN1;
363 }
364 PAddr >>= (pte->AddrShiftAmount - 12);
365 PAddr <<= pte->AddrShiftAmount;
366 PAddr |= (vaddr & pte->OffsetMask);
367 req->setPaddr(PAddr);
368 }
369 } else {
370 // Didn't find any match, return a TLB Refill Exception
389 ItbRefillFault *Flt = new ItbRefillFault();
390 /* EntryHi VPN, ASID fields must be set */
391 Flt->entryHiAsid = Asid;
392 Flt->entryHiVPN2 = (VPN >> 2);
393 Flt->entryHiVPN2X = (VPN & 0x3);
394
395 /* BadVAddr must be set */
396 Flt->badVAddr = vaddr;
397
398 /* Context must be set */
399 Flt->contextBadVPN2 = (VPN >> 2);
400 return Flt;
371 return new ItbRefillFault(Asid, vaddr, vpn);
401 }
402 }
403 return checkCacheability(req);
404#endif
405}
406
407Fault
408TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)

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432
433 bool misaligned = (req->getSize() - 1) & vaddr;
434
435 if (IsKSeg0(vaddr)) {
436 // Address will not be translated through TLB, set response, and go!
437 req->setPaddr(KSeg02Phys(vaddr));
438 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
439 misaligned) {
372 }
373 }
374 return checkCacheability(req);
375#endif
376}
377
378Fault
379TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)

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403
404 bool misaligned = (req->getSize() - 1) & vaddr;
405
406 if (IsKSeg0(vaddr)) {
407 // Address will not be translated through TLB, set response, and go!
408 req->setPaddr(KSeg02Phys(vaddr));
409 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
410 misaligned) {
440 StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
441 /* BadVAddr must be set */
442 Flt->badVAddr = vaddr;
443
444 return Flt;
411 return new StoreAddressErrorFault(vaddr);
445 }
446 } else if(IsKSeg1(vaddr)) {
447 // Address will not be translated through TLB, set response, and go!
448 req->setPaddr(KSeg02Phys(vaddr));
449 } else {
450 /*
451 * This is an optimization - smallPages is updated every time a TLB
452 * operation is performed. That way, we don't need to look at
453 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
454 */
455 Addr VPN = (vaddr >> 11) & 0xFFFFFFFC;
456 if (smallPages == 1) {
457 VPN = vaddr >> 11;
458 }
459 uint8_t Asid = req->getAsid();
460 PTE *pte = lookup(VPN, Asid);
461 if (misaligned) {
412 }
413 } else if(IsKSeg1(vaddr)) {
414 // Address will not be translated through TLB, set response, and go!
415 req->setPaddr(KSeg02Phys(vaddr));
416 } else {
417 /*
418 * This is an optimization - smallPages is updated every time a TLB
419 * operation is performed. That way, we don't need to look at
420 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
421 */
422 Addr VPN = (vaddr >> 11) & 0xFFFFFFFC;
423 if (smallPages == 1) {
424 VPN = vaddr >> 11;
425 }
426 uint8_t Asid = req->getAsid();
427 PTE *pte = lookup(VPN, Asid);
428 if (misaligned) {
462 // Unaligned address!
463 StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
464 /* BadVAddr must be set */
465 Flt->badVAddr = vaddr;
466 return Flt;
429 return new StoreAddressErrorFault(vaddr);
467 }
468 if (pte != NULL) {
469 // Ok, found something
470 /* Check for valid bits */
471 int EvenOdd;
472 bool Valid;
473 bool Dirty;
474 if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) {

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479 } else {
480 // Check odd bits
481 Valid = pte->V1;
482 Dirty = pte->D1;
483 EvenOdd = 1;
484 }
485
486 if (Valid == false) {
430 }
431 if (pte != NULL) {
432 // Ok, found something
433 /* Check for valid bits */
434 int EvenOdd;
435 bool Valid;
436 bool Dirty;
437 if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) {

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442 } else {
443 // Check odd bits
444 Valid = pte->V1;
445 Dirty = pte->D1;
446 EvenOdd = 1;
447 }
448
449 if (Valid == false) {
487 //Invalid entry
488 DtbInvalidFault *Flt = new DtbInvalidFault();
489 /* EntryHi VPN, ASID fields must be set */
490 Flt->entryHiAsid = Asid;
491 Flt->entryHiVPN2 = (VPN>>2);
492 Flt->entryHiVPN2X = (VPN & 0x3);
493
494 /* BadVAddr must be set */
495 Flt->badVAddr = vaddr;
496
497 /* Context must be set */
498 Flt->contextBadVPN2 = (VPN >> 2);
499
500 return Flt;
450 return new DtbInvalidFault(Asid, vaddr, VPN);
501 } else {
502 // Ok, this is really a match, set paddr
503 if (!Dirty) {
451 } else {
452 // Ok, this is really a match, set paddr
453 if (!Dirty) {
504 TLBModifiedFault *Flt = new TLBModifiedFault();
505 /* EntryHi VPN, ASID fields must be set */
506 Flt->entryHiAsid = Asid;
507 Flt->entryHiVPN2 = (VPN >> 2);
508 Flt->entryHiVPN2X = (VPN & 0x3);
509
510 /* BadVAddr must be set */
511 Flt->badVAddr = vaddr;
512
513 /* Context must be set */
514 Flt->contextBadVPN2 = (VPN >> 2);
515 return Flt;
454 return new TLBModifiedFault(Asid, vaddr, VPN);
516 }
517 Addr PAddr;
518 if (EvenOdd == 0) {
519 PAddr = pte->PFN0;
520 } else {
521 PAddr = pte->PFN1;
522 }
523 PAddr >>= (pte->AddrShiftAmount - 12);
524 PAddr <<= pte->AddrShiftAmount;
525 PAddr |= (vaddr & pte->OffsetMask);
526 req->setPaddr(PAddr);
527 }
528 } else {
529 // Didn't find any match, return a TLB Refill Exception
455 }
456 Addr PAddr;
457 if (EvenOdd == 0) {
458 PAddr = pte->PFN0;
459 } else {
460 PAddr = pte->PFN1;
461 }
462 PAddr >>= (pte->AddrShiftAmount - 12);
463 PAddr <<= pte->AddrShiftAmount;
464 PAddr |= (vaddr & pte->OffsetMask);
465 req->setPaddr(PAddr);
466 }
467 } else {
468 // Didn't find any match, return a TLB Refill Exception
530 DtbRefillFault *Flt = new DtbRefillFault();
531 /* EntryHi VPN, ASID fields must be set */
532 Flt->entryHiAsid = Asid;
533 Flt->entryHiVPN2 = (VPN >> 2);
534 Flt->entryHiVPN2X = (VPN & 0x3);
535
536 /* BadVAddr must be set */
537 Flt->badVAddr = vaddr;
538
539 /* Context must be set */
540 Flt->contextBadVPN2 = (VPN >> 2);
541 return Flt;
469 return new DtbRefillFault(Asid, vaddr, VPN);
542 }
543 }
544 return checkCacheability(req);
545#endif
546}
547
548Fault
549TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

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471 }
472 return checkCacheability(req);
473#endif
474}
475
476Fault
477TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

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