tlb.cc (5894:8091ac99341a) | tlb.cc (6022:410194bb3049) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include "arch/mips/faults.hh" 41#include "arch/mips/utility.hh" 42#include "base/inifile.hh" 43#include "base/str.hh" 44#include "base/trace.hh" 45#include "cpu/thread_context.hh" 46#include "sim/process.hh" 47#include "mem/page_table.hh" | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include "arch/mips/faults.hh" 41#include "arch/mips/utility.hh" 42#include "base/inifile.hh" 43#include "base/str.hh" 44#include "base/trace.hh" 45#include "cpu/thread_context.hh" 46#include "sim/process.hh" 47#include "mem/page_table.hh" |
48#include "params/MipsDTB.hh" 49#include "params/MipsITB.hh" | |
50#include "params/MipsTLB.hh" | 48#include "params/MipsTLB.hh" |
51#include "params/MipsUTB.hh" | |
52 53 54using namespace std; 55using namespace MipsISA; 56 57/////////////////////////////////////////////////////////////////////// 58// 59// MIPS TLB --- 245 unchanged lines hidden (view full) --- 305 ; 306 307 hits = read_hits + write_hits; 308 misses = read_misses + write_misses; 309 accesses = read_accesses + write_accesses; 310} 311 312Fault | 49 50 51using namespace std; 52using namespace MipsISA; 53 54/////////////////////////////////////////////////////////////////////// 55// 56// MIPS TLB --- 245 unchanged lines hidden (view full) --- 302 ; 303 304 hits = read_hits + write_hits; 305 misses = read_misses + write_misses; 306 accesses = read_accesses + write_accesses; 307} 308 309Fault |
313ITB::translateAtomic(RequestPtr req, ThreadContext *tc) | 310TLB::translateInst(RequestPtr req, ThreadContext *tc) |
314{ 315#if !FULL_SYSTEM 316 Process * p = tc->getProcessPtr(); 317 318 Fault fault = p->pTable->translate(req); 319 if(fault != NoFault) 320 return fault; 321 --- 99 unchanged lines hidden (view full) --- 421 Flt->Context_BadVPN2 = (VPN >> 2); 422 return Flt; 423 } 424 } 425 return checkCacheability(req); 426#endif 427} 428 | 311{ 312#if !FULL_SYSTEM 313 Process * p = tc->getProcessPtr(); 314 315 Fault fault = p->pTable->translate(req); 316 if(fault != NoFault) 317 return fault; 318 --- 99 unchanged lines hidden (view full) --- 418 Flt->Context_BadVPN2 = (VPN >> 2); 419 return Flt; 420 } 421 } 422 return checkCacheability(req); 423#endif 424} 425 |
429void 430ITB::translateTiming(RequestPtr req, ThreadContext *tc, 431 Translation *translation) 432{ 433 assert(translation); 434 translation->finish(translateAtomic(req, tc), req, tc, false); 435} 436 | |
437Fault | 426Fault |
438DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write) | 427TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) |
439{ 440#if !FULL_SYSTEM 441 Process * p = tc->getProcessPtr(); 442 443 Fault fault = p->pTable->translate(req); 444 if(fault != NoFault) 445 return fault; 446 --- 120 unchanged lines hidden (view full) --- 567 Flt->Context_BadVPN2 = (VPN >> 2); 568 return Flt; 569 } 570 } 571 return checkCacheability(req); 572#endif 573} 574 | 428{ 429#if !FULL_SYSTEM 430 Process * p = tc->getProcessPtr(); 431 432 Fault fault = p->pTable->translate(req); 433 if(fault != NoFault) 434 return fault; 435 --- 120 unchanged lines hidden (view full) --- 556 Flt->Context_BadVPN2 = (VPN >> 2); 557 return Flt; 558 } 559 } 560 return checkCacheability(req); 561#endif 562} 563 |
564Fault 565TLB::translateAtomic(RequestPtr req, ThreadContext *tc, 566 bool write, bool execute) 567{ 568 if (execute) 569 return translateInst(req, tc); 570 else 571 return translateData(req, tc, write); 572} 573 |
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575void | 574void |
576DTB::translateTiming(RequestPtr req, ThreadContext *tc, 577 Translation *translation, bool write) | 575TLB::translateTiming(RequestPtr req, ThreadContext *tc, 576 Translation *translation, bool write, bool execute) |
578{ 579 assert(translation); | 577{ 578 assert(translation); |
580 translation->finish(translateAtomic(req, tc, write), req, tc, write); | 579 translation->finish(translateAtomic(req, tc, write, execute), 580 req, tc, write, execute); |
581} 582 | 581} 582 |
583/////////////////////////////////////////////////////////////////////// 584// 585// Mips ITB 586// 587ITB::ITB(const Params *p) 588 : TLB(p) 589{} | |
590 | 583 |
591 592// void 593// ITB::regStats() 594// { 595// /* hits - causes failure for some reason 596// .name(name() + ".hits") 597// .desc("ITB hits"); 598// misses 599// .name(name() + ".misses") 600// .desc("ITB misses"); 601// acv 602// .name(name() + ".acv") 603// .desc("ITB acv"); 604// accesses 605// .name(name() + ".accesses") 606// .desc("ITB accesses"); 607 608// accesses = hits + misses + invalids; */ 609// } 610 611 612 613/////////////////////////////////////////////////////////////////////// 614// 615// Mips DTB 616// 617DTB::DTB(const Params *p) 618 : TLB(p) 619{} 620 621/////////////////////////////////////////////////////////////////////// 622// 623// Mips UTB 624// 625UTB::UTB(const Params *p) 626 : ITB(p), DTB(p) 627{} 628 629 630 | |
631MipsISA::PTE & 632TLB::index(bool advance) 633{ 634 MipsISA::PTE *pte = &table[nlu]; 635 636 if (advance) 637 nextnlu(); 638 639 return *pte; 640} 641 | 584MipsISA::PTE & 585TLB::index(bool advance) 586{ 587 MipsISA::PTE *pte = &table[nlu]; 588 589 if (advance) 590 nextnlu(); 591 592 return *pte; 593} 594 |
642MipsISA::ITB * 643MipsITBParams::create() | 595MipsISA::TLB * 596MipsTLBParams::create() |
644{ | 597{ |
645 return new MipsISA::ITB(this); | 598 return new MipsISA::TLB(this); |
646} | 599} |
647 648MipsISA::DTB * 649MipsDTBParams::create() 650{ 651 return new MipsISA::DTB(this); 652} 653 654MipsISA::UTB * 655MipsUTBParams::create() 656{ 657 return new MipsISA::UTB(this); 658} | |