tlb.cc (5543:3af77710f397) tlb.cc (5736:426510e758ad)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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144Fault inline
145TLB::checkCacheability(RequestPtr &req)
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual address
149 // or by the TLB entry
150 if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 135 unchanged lines hidden (view full) ---

144Fault inline
145TLB::checkCacheability(RequestPtr &req)
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual address
149 // or by the TLB entry
150 if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
152 req->setFlags(req->getFlags() | UNCACHEABLE);
152 req->setFlags(Request::UNCACHEABLE);
153 }
154 return NoFault;
155}
156void TLB::insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages)
157{
158 smallPages=_smallPages;
159 if(Index > size){
160 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);

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153 }
154 return NoFault;
155}
156void TLB::insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages)
157{
158 smallPages=_smallPages;
159 if(Index > size){
160 warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);

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