tlb.cc (5358:e9acb84bbafb) | tlb.cc (5543:3af77710f397) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 45 unchanged lines hidden (view full) --- 54using namespace std; 55using namespace MipsISA; 56 57/////////////////////////////////////////////////////////////////////// 58// 59// MIPS TLB 60// 61 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 45 unchanged lines hidden (view full) --- 54using namespace std; 55using namespace MipsISA; 56 57/////////////////////////////////////////////////////////////////////// 58// 59// MIPS TLB 60// 61 |
62#define MODE2MASK(X) (1 << (X)) | 62#define MODE2MASK(X) (1 << (X)) |
63 64TLB::TLB(const Params *p) 65 : BaseTLB(p), size(p->size), nlu(0) 66{ 67 table = new MipsISA::PTE[size]; 68 memset(table, 0, sizeof(MipsISA::PTE[size])); 69 smallPages=0; 70} --- 15 unchanged lines hidden (view full) --- 86 while (i->first == vpn) { 87 int index = i->second; 88 MipsISA::PTE *pte = &table[index]; 89 90 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 91 Addr Mask = pte->Mask; 92 Addr InvMask = ~Mask; 93 Addr VPN = pte->VPN; | 63 64TLB::TLB(const Params *p) 65 : BaseTLB(p), size(p->size), nlu(0) 66{ 67 table = new MipsISA::PTE[size]; 68 memset(table, 0, sizeof(MipsISA::PTE[size])); 69 smallPages=0; 70} --- 15 unchanged lines hidden (view full) --- 86 while (i->first == vpn) { 87 int index = i->second; 88 MipsISA::PTE *pte = &table[index]; 89 90 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */ 91 Addr Mask = pte->Mask; 92 Addr InvMask = ~Mask; 93 Addr VPN = pte->VPN; |
94 // warn("Valid: %d - %d\n",pte->V0,pte->V1); | 94 // warn("Valid: %d - %d\n",pte->V0,pte->V1); |
95 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 96 { // We have a VPN + ASID Match 97 retval = pte; 98 break; 99 } 100 ++i; 101 } 102 } --- 281 unchanged lines hidden (view full) --- 384 Flt->BadVAddr = req->getVaddr(); 385 386 /* Context must be set */ 387 Flt->Context_BadVPN2 = (VPN >> 2); 388 return Flt; 389 } 390 else 391 {// Ok, this is really a match, set paddr | 95 if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) 96 { // We have a VPN + ASID Match 97 retval = pte; 98 break; 99 } 100 ++i; 101 } 102 } --- 281 unchanged lines hidden (view full) --- 384 Flt->BadVAddr = req->getVaddr(); 385 386 /* Context must be set */ 387 Flt->Context_BadVPN2 = (VPN >> 2); 388 return Flt; 389 } 390 else 391 {// Ok, this is really a match, set paddr |
392 // hits++; | 392 // hits++; |
393 Addr PAddr; 394 if(EvenOdd == 0){ 395 PAddr = pte->PFN0; 396 }else{ 397 PAddr = pte->PFN1; 398 } 399 PAddr >>= (pte->AddrShiftAmount-12); 400 PAddr <<= pte->AddrShiftAmount; 401 PAddr |= ((req->getVaddr()) & pte->OffsetMask); 402 req->setPaddr(PAddr); 403 404 405 } 406 } 407 else 408 { // Didn't find any match, return a TLB Refill Exception | 393 Addr PAddr; 394 if(EvenOdd == 0){ 395 PAddr = pte->PFN0; 396 }else{ 397 PAddr = pte->PFN1; 398 } 399 PAddr >>= (pte->AddrShiftAmount-12); 400 PAddr <<= pte->AddrShiftAmount; 401 PAddr |= ((req->getVaddr()) & pte->OffsetMask); 402 req->setPaddr(PAddr); 403 404 405 } 406 } 407 else 408 { // Didn't find any match, return a TLB Refill Exception |
409 // misses++; | 409 // misses++; |
410 ItbRefillFault *Flt=new ItbRefillFault(); 411 /* EntryHi VPN, ASID fields must be set */ 412 Flt->EntryHi_Asid = Asid; 413 Flt->EntryHi_VPN2 = (VPN>>2); 414 Flt->EntryHi_VPN2X = (VPN & 0x3); 415 416 417 /* BadVAddr must be set */ --- 71 unchanged lines hidden (view full) --- 489 // Check odd bits 490 Valid = pte->V1; 491 Dirty = pte->D1; 492 EvenOdd = 1; 493 } 494 495 if(Valid == false) 496 {//Invalid entry | 410 ItbRefillFault *Flt=new ItbRefillFault(); 411 /* EntryHi VPN, ASID fields must be set */ 412 Flt->EntryHi_Asid = Asid; 413 Flt->EntryHi_VPN2 = (VPN>>2); 414 Flt->EntryHi_VPN2X = (VPN & 0x3); 415 416 417 /* BadVAddr must be set */ --- 71 unchanged lines hidden (view full) --- 489 // Check odd bits 490 Valid = pte->V1; 491 Dirty = pte->D1; 492 EvenOdd = 1; 493 } 494 495 if(Valid == false) 496 {//Invalid entry |
497 // invalids++; | 497 // invalids++; |
498 DtbInvalidFault *Flt = new DtbInvalidFault(); 499 /* EntryHi VPN, ASID fields must be set */ 500 Flt->EntryHi_Asid = Asid; 501 Flt->EntryHi_VPN2 = (VPN>>2); 502 Flt->EntryHi_VPN2X = (VPN & 0x3); 503 504 505 /* BadVAddr must be set */ 506 Flt->BadVAddr = req->getVaddr(); 507 508 /* Context must be set */ 509 Flt->Context_BadVPN2 = (VPN >> 2); 510 511 return Flt; 512 } 513 else 514 {// Ok, this is really a match, set paddr | 498 DtbInvalidFault *Flt = new DtbInvalidFault(); 499 /* EntryHi VPN, ASID fields must be set */ 500 Flt->EntryHi_Asid = Asid; 501 Flt->EntryHi_VPN2 = (VPN>>2); 502 Flt->EntryHi_VPN2X = (VPN & 0x3); 503 504 505 /* BadVAddr must be set */ 506 Flt->BadVAddr = req->getVaddr(); 507 508 /* Context must be set */ 509 Flt->Context_BadVPN2 = (VPN >> 2); 510 511 return Flt; 512 } 513 else 514 {// Ok, this is really a match, set paddr |
515 // hits++; | 515 // hits++; |
516 if(!Dirty) 517 { 518 TLBModifiedFault *Flt = new TLBModifiedFault(); 519 /* EntryHi VPN, ASID fields must be set */ 520 Flt->EntryHi_Asid = Asid; 521 Flt->EntryHi_VPN2 = (VPN>>2); 522 Flt->EntryHi_VPN2X = (VPN & 0x3); 523 --- 15 unchanged lines hidden (view full) --- 539 PAddr >>= (pte->AddrShiftAmount-12); 540 PAddr <<= pte->AddrShiftAmount; 541 PAddr |= ((req->getVaddr()) & pte->OffsetMask); 542 req->setPaddr(PAddr); 543 } 544 } 545 else 546 { // Didn't find any match, return a TLB Refill Exception | 516 if(!Dirty) 517 { 518 TLBModifiedFault *Flt = new TLBModifiedFault(); 519 /* EntryHi VPN, ASID fields must be set */ 520 Flt->EntryHi_Asid = Asid; 521 Flt->EntryHi_VPN2 = (VPN>>2); 522 Flt->EntryHi_VPN2X = (VPN & 0x3); 523 --- 15 unchanged lines hidden (view full) --- 539 PAddr >>= (pte->AddrShiftAmount-12); 540 PAddr <<= pte->AddrShiftAmount; 541 PAddr |= ((req->getVaddr()) & pte->OffsetMask); 542 req->setPaddr(PAddr); 543 } 544 } 545 else 546 { // Didn't find any match, return a TLB Refill Exception |
547 // misses++; | 547 // misses++; |
548 DtbRefillFault *Flt=new DtbRefillFault(); 549 /* EntryHi VPN, ASID fields must be set */ 550 Flt->EntryHi_Asid = Asid; 551 Flt->EntryHi_VPN2 = (VPN>>2); 552 Flt->EntryHi_VPN2X = (VPN & 0x3); 553 554 555 /* BadVAddr must be set */ --- 16 unchanged lines hidden (view full) --- 572 : TLB(p) 573{} 574 575 576// void 577// ITB::regStats() 578// { 579// /* hits - causes failure for some reason | 548 DtbRefillFault *Flt=new DtbRefillFault(); 549 /* EntryHi VPN, ASID fields must be set */ 550 Flt->EntryHi_Asid = Asid; 551 Flt->EntryHi_VPN2 = (VPN>>2); 552 Flt->EntryHi_VPN2X = (VPN & 0x3); 553 554 555 /* BadVAddr must be set */ --- 16 unchanged lines hidden (view full) --- 572 : TLB(p) 573{} 574 575 576// void 577// ITB::regStats() 578// { 579// /* hits - causes failure for some reason |
580// .name(name() + ".hits") 581// .desc("ITB hits"); | 580// .name(name() + ".hits") 581// .desc("ITB hits"); |
582// misses | 582// misses |
583// .name(name() + ".misses") 584// .desc("ITB misses"); | 583// .name(name() + ".misses") 584// .desc("ITB misses"); |
585// acv | 585// acv |
586// .name(name() + ".acv") 587// .desc("ITB acv"); | 586// .name(name() + ".acv") 587// .desc("ITB acv"); |
588// accesses | 588// accesses |
589// .name(name() + ".accesses") 590// .desc("ITB accesses"); | 589// .name(name() + ".accesses") 590// .desc("ITB accesses"); |
591 | 591 |
592// accesses = hits + misses + invalids; */ | 592// accesses = hits + misses + invalids; */ |
593// } 594 595 596 597/////////////////////////////////////////////////////////////////////// 598// 599// Mips DTB 600// --- 42 unchanged lines hidden --- | 593// } 594 595 596 597/////////////////////////////////////////////////////////////////////// 598// 599// Mips DTB 600// --- 42 unchanged lines hidden --- |