tlb.cc (5222:bb733a878f85) tlb.cc (5224:0e354459fb8a)
1/*
2 * Copyright 2007 MIPS Technologies, Inc. All Rights Reserved
3 *
4 * This software is part of the M5 simulator.
5 *
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.

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42#include "arch/mips/pagetable.hh"
43#include "arch/mips/tlb.hh"
44#include "arch/mips/faults.hh"
45#include "arch/mips/utility.hh"
46#include "base/inifile.hh"
47#include "base/str.hh"
48#include "base/trace.hh"
49#include "cpu/thread_context.hh"
1/*
2 * Copyright 2007 MIPS Technologies, Inc. All Rights Reserved
3 *
4 * This software is part of the M5 simulator.
5 *
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.

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42#include "arch/mips/pagetable.hh"
43#include "arch/mips/tlb.hh"
44#include "arch/mips/faults.hh"
45#include "arch/mips/utility.hh"
46#include "base/inifile.hh"
47#include "base/str.hh"
48#include "base/trace.hh"
49#include "cpu/thread_context.hh"
50#include "sim/process.hh"
51#include "mem/page_table.hh"
50#include "params/MipsDTB.hh"
51#include "params/MipsITB.hh"
52#include "params/MipsTLB.hh"
53#include "params/MipsUTB.hh"
54
55
56using namespace std;
57using namespace MipsISA;

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309 hits = read_hits + write_hits;
310 misses = read_misses + write_misses;
311 accesses = read_accesses + write_accesses;
312}
313
314Fault
315ITB::translate(RequestPtr &req, ThreadContext *tc)
316{
52#include "params/MipsDTB.hh"
53#include "params/MipsITB.hh"
54#include "params/MipsTLB.hh"
55#include "params/MipsUTB.hh"
56
57
58using namespace std;
59using namespace MipsISA;

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311 hits = read_hits + write_hits;
312 misses = read_misses + write_misses;
313 accesses = read_accesses + write_accesses;
314}
315
316Fault
317ITB::translate(RequestPtr &req, ThreadContext *tc)
318{
319#if !FULL_SYSTEM
320 Process * p = tc->getProcessPtr();
321
322 Fault fault = p->pTable->translate(req);
323 if(fault != NoFault)
324 return fault;
325
326 return NoFault;
327#else
317 if(MipsISA::IsKSeg0(req->getVaddr()))
318 {
319 // Address will not be translated through TLB, set response, and go!
320 req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
321 if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
322 {
323 AddressErrorFault *Flt = new AddressErrorFault();
324 /* BadVAddr must be set */

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411 Flt->BadVAddr = req->getVaddr();
412
413 /* Context must be set */
414 Flt->Context_BadVPN2 = (VPN >> 2);
415 return Flt;
416 }
417 }
418 return checkCacheability(req);
328 if(MipsISA::IsKSeg0(req->getVaddr()))
329 {
330 // Address will not be translated through TLB, set response, and go!
331 req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
332 if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
333 {
334 AddressErrorFault *Flt = new AddressErrorFault();
335 /* BadVAddr must be set */

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422 Flt->BadVAddr = req->getVaddr();
423
424 /* Context must be set */
425 Flt->Context_BadVPN2 = (VPN >> 2);
426 return Flt;
427 }
428 }
429 return checkCacheability(req);
430#endif
419}
420
421Fault
422DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
423{
431}
432
433Fault
434DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
435{
436#if !FULL_SYSTEM
437 Process * p = tc->getProcessPtr();
438
439 Fault fault = p->pTable->translate(req);
440 if(fault != NoFault)
441 return fault;
442
443 return NoFault;
444#else
424 if(MipsISA::IsKSeg0(req->getVaddr()))
425 {
426 // Address will not be translated through TLB, set response, and go!
427 req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
428 if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
429 {
430 StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
431 /* BadVAddr must be set */

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539 Flt->BadVAddr = req->getVaddr();
540
541 /* Context must be set */
542 Flt->Context_BadVPN2 = (VPN >> 2);
543 return Flt;
544 }
545 }
546 return checkCacheability(req);
445 if(MipsISA::IsKSeg0(req->getVaddr()))
446 {
447 // Address will not be translated through TLB, set response, and go!
448 req->setPaddr(MipsISA::KSeg02Phys(req->getVaddr()));
449 if(MipsISA::getOperatingMode(tc->readMiscReg(MipsISA::Status)) != mode_kernel || req->isMisaligned())
450 {
451 StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
452 /* BadVAddr must be set */

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560 Flt->BadVAddr = req->getVaddr();
561
562 /* Context must be set */
563 Flt->Context_BadVPN2 = (VPN >> 2);
564 return Flt;
565 }
566 }
567 return checkCacheability(req);
568#endif
547}
548
549///////////////////////////////////////////////////////////////////////
550//
551// Mips ITB
552//
553ITB::ITB(const Params *p)
554 : TLB(p)

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570
571///////////////////////////////////////////////////////////////////////
572//
573// Mips ITB
574//
575ITB::ITB(const Params *p)
576 : TLB(p)

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