tlb.cc (12406:86bde4a026b5) tlb.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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137 ++i;
138 }
139 }
140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
141 return Ind;
142}
143
144inline Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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137 ++i;
138 }
139 }
140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
141 return Ind;
142}
143
144inline Fault
145TLB::checkCacheability(RequestPtr &req)
145TLB::checkCacheability(const RequestPtr &req)
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual
149 // address or by the TLB entry
150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
153 }

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277 ;
278
279 hits = read_hits + write_hits;
280 misses = read_misses + write_misses;
281 accesses = read_accesses + write_accesses;
282}
283
284Fault
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual
149 // address or by the TLB entry
150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
153 }

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277 ;
278
279 hits = read_hits + write_hits;
280 misses = read_misses + write_misses;
281 accesses = read_accesses + write_accesses;
282}
283
284Fault
285TLB::translateInst(RequestPtr req, ThreadContext *tc)
285TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
286{
287 if (FullSystem)
288 panic("translateInst not implemented in MIPS.\n");
289
290 Process * p = tc->getProcessPtr();
291
292 Fault fault = p->pTable->translate(req);
293 if (fault != NoFault)
294 return fault;
295
296 return NoFault;
297}
298
299Fault
286{
287 if (FullSystem)
288 panic("translateInst not implemented in MIPS.\n");
289
290 Process * p = tc->getProcessPtr();
291
292 Fault fault = p->pTable->translate(req);
293 if (fault != NoFault)
294 return fault;
295
296 return NoFault;
297}
298
299Fault
300TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
300TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
301{
302 if (FullSystem)
303 panic("translateData not implemented in MIPS.\n");
304
305 Process * p = tc->getProcessPtr();
306
307 Fault fault = p->pTable->translate(req);
308 if (fault != NoFault)
309 return fault;
310
311 return NoFault;
312}
313
314Fault
301{
302 if (FullSystem)
303 panic("translateData not implemented in MIPS.\n");
304
305 Process * p = tc->getProcessPtr();
306
307 Fault fault = p->pTable->translate(req);
308 if (fault != NoFault)
309 return fault;
310
311 return NoFault;
312}
313
314Fault
315TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
315TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
316{
317 if (mode == Execute)
318 return translateInst(req, tc);
319 else
320 return translateData(req, tc, mode == Write);
321}
322
323void
316{
317 if (mode == Execute)
318 return translateInst(req, tc);
319 else
320 return translateData(req, tc, mode == Write);
321}
322
323void
324TLB::translateTiming(RequestPtr req, ThreadContext *tc,
324TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
325 Translation *translation, Mode mode)
326{
327 assert(translation);
328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
329}
330
331Fault
325 Translation *translation, Mode mode)
326{
327 assert(translation);
328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
329}
330
331Fault
332TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
332TLB::finalizePhysical(const RequestPtr &req,
333 ThreadContext *tc, Mode mode) const
333{
334 return NoFault;
335}
336
337
338MipsISA::PTE &
339TLB::index(bool advance)
340{

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335 return NoFault;
336}
337
338
339MipsISA::PTE &
340TLB::index(bool advance)
341{

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