1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 299 unchanged lines hidden (view full) --- 308 309 bool misaligned = (req->getSize() - 1) & vaddr; 310 311 if (IsKSeg0(vaddr)) { 312 // Address will not be translated through TLB, set response, and go! 313 req->setPaddr(KSeg02Phys(vaddr)); 314 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || 315 misaligned) { |
316 return new AddressErrorFault(vaddr, false); |
317 } 318 } else if(IsKSeg1(vaddr)) { 319 // Address will not be translated through TLB, set response, and go! 320 req->setPaddr(KSeg02Phys(vaddr)); 321 } else { 322 /* 323 * This is an optimization - smallPages is updated every time a TLB 324 * operation is performed. That way, we don't need to look at 325 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 326 */ 327 Addr VPN; 328 if (smallPages == 1) { 329 VPN = (vaddr >> 11); 330 } else { 331 VPN = ((vaddr >> 11) & 0xFFFFFFFC); 332 } 333 uint8_t Asid = req->getAsid(); 334 if (misaligned) { 335 // Unaligned address! |
336 return new AddressErrorFault(vaddr, false); |
337 } 338 PTE *pte = lookup(VPN,Asid); 339 if (pte != NULL) { 340 // Ok, found something 341 /* Check for valid bits */ 342 int EvenOdd; 343 bool Valid; 344 if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) { --- 37 unchanged lines hidden (view full) --- 382 //@TODO: This should actually use TLB instead of going directly 383 // to the page table in syscall mode. 384 /** 385 * Check for alignment faults 386 */ 387 if (req->getVaddr() & (req->getSize() - 1)) { 388 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 389 req->getSize()); |
390 return new AddressErrorFault(req->getVaddr(), write); |
391 } 392 393 394 Process * p = tc->getProcessPtr(); 395 396 Fault fault = p->pTable->translate(req); 397 if (fault != NoFault) 398 return fault; --- 4 unchanged lines hidden (view full) --- 403 404 bool misaligned = (req->getSize() - 1) & vaddr; 405 406 if (IsKSeg0(vaddr)) { 407 // Address will not be translated through TLB, set response, and go! 408 req->setPaddr(KSeg02Phys(vaddr)); 409 if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel || 410 misaligned) { |
411 return new AddressErrorFault(vaddr, true); |
412 } 413 } else if(IsKSeg1(vaddr)) { 414 // Address will not be translated through TLB, set response, and go! 415 req->setPaddr(KSeg02Phys(vaddr)); 416 } else { 417 /* 418 * This is an optimization - smallPages is updated every time a TLB 419 * operation is performed. That way, we don't need to look at 420 * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup 421 */ 422 Addr VPN = (vaddr >> 11) & 0xFFFFFFFC; 423 if (smallPages == 1) { 424 VPN = vaddr >> 11; 425 } 426 uint8_t Asid = req->getAsid(); 427 PTE *pte = lookup(VPN, Asid); 428 if (misaligned) { |
429 return new AddressErrorFault(vaddr, true); |
430 } 431 if (pte != NULL) { 432 // Ok, found something 433 /* Check for valid bits */ 434 int EvenOdd; 435 bool Valid; 436 bool Dirty; 437 if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) { --- 72 unchanged lines hidden --- |