1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include <string>
37#include <vector>
38
39#include "arch/mips/faults.hh"
40#include "arch/mips/pagetable.hh"
41#include "arch/mips/pra_constants.hh"
42#include "arch/mips/tlb.hh"
43#include "arch/mips/utility.hh"
44#include "base/inifile.hh"
45#include "base/str.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/MipsPRA.hh"
49#include "debug/TLB.hh"
50#include "mem/page_table.hh"
51#include "params/MipsTLB.hh"
52#include "sim/process.hh"
53
54using namespace std;
55using namespace MipsISA;
56
57///////////////////////////////////////////////////////////////////////
58//
59// MIPS TLB
60//
61
62static inline mode_type
63getOperatingMode(MiscReg Stat)
64{
65 if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
66 return mode_kernel;
67 } else if ((Stat & 0x18) == 0x8) {
68 return mode_supervisor;
69 } else if ((Stat & 0x18) == 0x10) {
70 return mode_user;
71 } else {
72 return mode_number;
73 }
74}
75
76
77TLB::TLB(const Params *p)
78 : BaseTLB(p), size(p->size), nlu(0)
79{
80 table = new PTE[size];
81 memset(table, 0, sizeof(PTE[size]));
82 smallPages = 0;
83}
84
85TLB::~TLB()
86{
87 if (table)
88 delete [] table;
89}
90
91// look up an entry in the TLB
92MipsISA::PTE *
93TLB::lookup(Addr vpn, uint8_t asn) const
94{
95 // assume not found...
96 PTE *retval = NULL;
97 PageTable::const_iterator i = lookupTable.find(vpn);
98 if (i != lookupTable.end()) {
99 while (i->first == vpn) {
100 int index = i->second;
101 PTE *pte = &table[index];
102
103 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
104 Addr Mask = pte->Mask;
105 Addr InvMask = ~Mask;
106 Addr VPN = pte->VPN;
107 if (((vpn & InvMask) == (VPN & InvMask)) &&
108 (pte->G || (asn == pte->asid))) {
109 // We have a VPN + ASID Match
110 retval = pte;
111 break;
112 }
113 ++i;
114 }
115 }
116
117 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
118 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
119 return retval;
120}
121
122MipsISA::PTE*
123TLB::getEntry(unsigned Index) const
124{
125 // Make sure that Index is valid
126 assert(Index<size);
127 return &table[Index];
128}
129
130int
131TLB::probeEntry(Addr vpn, uint8_t asn) const
132{
133 // assume not found...
134 int Ind = -1;
135 PageTable::const_iterator i = lookupTable.find(vpn);
136 if (i != lookupTable.end()) {
137 while (i->first == vpn) {
138 int index = i->second;
139 PTE *pte = &table[index];
140
141 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
142 Addr Mask = pte->Mask;
143 Addr InvMask = ~Mask;
144 Addr VPN = pte->VPN;
145 if (((vpn & InvMask) == (VPN & InvMask)) &&
146 (pte->G || (asn == pte->asid))) {
147 // We have a VPN + ASID Match
148 Ind = index;
149 break;
150 }
151 ++i;
152 }
153 }
154 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
155 return Ind;
156}
157
158inline Fault
159TLB::checkCacheability(RequestPtr &req)
160{
161 Addr VAddrUncacheable = 0xA0000000;
162 // In MIPS, cacheability is controlled by certain bits of the virtual
163 // address or by the TLB entry
164 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
165 // mark request as uncacheable
166 req->setFlags(Request::UNCACHEABLE);
167 }
168 return NoFault;
169}
170
171void
172TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
173{
174 smallPages = _smallPages;
175 if (Index > size) {
176 warn("Attempted to write at index (%d) beyond TLB size (%d)",
177 Index, size);
178 } else {
179 // Update TLB
180 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
181 Index, pte.Mask << 11,
182 ((pte.VPN << 11) | pte.asid),
183 ((pte.PFN0 << 6) | (pte.C0 << 3) |
184 (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
185 ((pte.PFN1 <<6) | (pte.C1 << 3) |
186 (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include <string>
37#include <vector>
38
39#include "arch/mips/faults.hh"
40#include "arch/mips/pagetable.hh"
41#include "arch/mips/pra_constants.hh"
42#include "arch/mips/tlb.hh"
43#include "arch/mips/utility.hh"
44#include "base/inifile.hh"
45#include "base/str.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/MipsPRA.hh"
49#include "debug/TLB.hh"
50#include "mem/page_table.hh"
51#include "params/MipsTLB.hh"
52#include "sim/process.hh"
53
54using namespace std;
55using namespace MipsISA;
56
57///////////////////////////////////////////////////////////////////////
58//
59// MIPS TLB
60//
61
62static inline mode_type
63getOperatingMode(MiscReg Stat)
64{
65 if ((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) {
66 return mode_kernel;
67 } else if ((Stat & 0x18) == 0x8) {
68 return mode_supervisor;
69 } else if ((Stat & 0x18) == 0x10) {
70 return mode_user;
71 } else {
72 return mode_number;
73 }
74}
75
76
77TLB::TLB(const Params *p)
78 : BaseTLB(p), size(p->size), nlu(0)
79{
80 table = new PTE[size];
81 memset(table, 0, sizeof(PTE[size]));
82 smallPages = 0;
83}
84
85TLB::~TLB()
86{
87 if (table)
88 delete [] table;
89}
90
91// look up an entry in the TLB
92MipsISA::PTE *
93TLB::lookup(Addr vpn, uint8_t asn) const
94{
95 // assume not found...
96 PTE *retval = NULL;
97 PageTable::const_iterator i = lookupTable.find(vpn);
98 if (i != lookupTable.end()) {
99 while (i->first == vpn) {
100 int index = i->second;
101 PTE *pte = &table[index];
102
103 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
104 Addr Mask = pte->Mask;
105 Addr InvMask = ~Mask;
106 Addr VPN = pte->VPN;
107 if (((vpn & InvMask) == (VPN & InvMask)) &&
108 (pte->G || (asn == pte->asid))) {
109 // We have a VPN + ASID Match
110 retval = pte;
111 break;
112 }
113 ++i;
114 }
115 }
116
117 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
118 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
119 return retval;
120}
121
122MipsISA::PTE*
123TLB::getEntry(unsigned Index) const
124{
125 // Make sure that Index is valid
126 assert(Index<size);
127 return &table[Index];
128}
129
130int
131TLB::probeEntry(Addr vpn, uint8_t asn) const
132{
133 // assume not found...
134 int Ind = -1;
135 PageTable::const_iterator i = lookupTable.find(vpn);
136 if (i != lookupTable.end()) {
137 while (i->first == vpn) {
138 int index = i->second;
139 PTE *pte = &table[index];
140
141 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
142 Addr Mask = pte->Mask;
143 Addr InvMask = ~Mask;
144 Addr VPN = pte->VPN;
145 if (((vpn & InvMask) == (VPN & InvMask)) &&
146 (pte->G || (asn == pte->asid))) {
147 // We have a VPN + ASID Match
148 Ind = index;
149 break;
150 }
151 ++i;
152 }
153 }
154 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
155 return Ind;
156}
157
158inline Fault
159TLB::checkCacheability(RequestPtr &req)
160{
161 Addr VAddrUncacheable = 0xA0000000;
162 // In MIPS, cacheability is controlled by certain bits of the virtual
163 // address or by the TLB entry
164 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
165 // mark request as uncacheable
166 req->setFlags(Request::UNCACHEABLE);
167 }
168 return NoFault;
169}
170
171void
172TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
173{
174 smallPages = _smallPages;
175 if (Index > size) {
176 warn("Attempted to write at index (%d) beyond TLB size (%d)",
177 Index, size);
178 } else {
179 // Update TLB
180 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
181 Index, pte.Mask << 11,
182 ((pte.VPN << 11) | pte.asid),
183 ((pte.PFN0 << 6) | (pte.C0 << 3) |
184 (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
185 ((pte.PFN1 <<6) | (pte.C1 << 3) |
186 (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
|
188 // Previous entry is valid
189 PageTable::iterator i = lookupTable.find(table[Index].VPN);
190 lookupTable.erase(i);
191 }
192 table[Index]=pte;
193 // Update fast lookup table
194 lookupTable.insert(make_pair(table[Index].VPN, Index));
195 }
196}
197
198// insert a new TLB entry
199void
200TLB::insert(Addr addr, PTE &pte)
201{
202 fatal("TLB Insert not yet implemented\n");
203}
204
205void
206TLB::flushAll()
207{
208 DPRINTF(TLB, "flushAll\n");
209 memset(table, 0, sizeof(PTE[size]));
210 lookupTable.clear();
211 nlu = 0;
212}
213
214void
215TLB::serialize(ostream &os)
216{
217 SERIALIZE_SCALAR(size);
218 SERIALIZE_SCALAR(nlu);
219
220 for (int i = 0; i < size; i++) {
221 nameOut(os, csprintf("%s.PTE%d", name(), i));
222 table[i].serialize(os);
223 }
224}
225
226void
227TLB::unserialize(Checkpoint *cp, const string §ion)
228{
229 UNSERIALIZE_SCALAR(size);
230 UNSERIALIZE_SCALAR(nlu);
231
232 for (int i = 0; i < size; i++) {
233 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
234 if (table[i].V0 || table[i].V1) {
235 lookupTable.insert(make_pair(table[i].VPN, i));
236 }
237 }
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295Fault
296TLB::translateInst(RequestPtr req, ThreadContext *tc)
297{
298 if (FullSystem)
299 panic("translateInst not implemented in MIPS.\n");
300
301 Process * p = tc->getProcessPtr();
302
303 Fault fault = p->pTable->translate(req);
304 if (fault != NoFault)
305 return fault;
306
307 return NoFault;
308}
309
310Fault
311TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
312{
313 if (FullSystem)
314 panic("translateData not implemented in MIPS.\n");
315
316 Process * p = tc->getProcessPtr();
317
318 Fault fault = p->pTable->translate(req);
319 if (fault != NoFault)
320 return fault;
321
322 return NoFault;
323}
324
325Fault
326TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
327{
328 if (mode == Execute)
329 return translateInst(req, tc);
330 else
331 return translateData(req, tc, mode == Write);
332}
333
334void
335TLB::translateTiming(RequestPtr req, ThreadContext *tc,
336 Translation *translation, Mode mode)
337{
338 assert(translation);
339 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
340}
341
342Fault
343TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
344{
345 panic("Not implemented\n");
346 return NoFault;
347}
348
349Fault
350TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
351{
352 return NoFault;
353}
354
355
356MipsISA::PTE &
357TLB::index(bool advance)
358{
359 PTE *pte = &table[nlu];
360
361 if (advance)
362 nextnlu();
363
364 return *pte;
365}
366
367MipsISA::TLB *
368MipsTLBParams::create()
369{
370 return new TLB(this);
371}
| 188 // Previous entry is valid
189 PageTable::iterator i = lookupTable.find(table[Index].VPN);
190 lookupTable.erase(i);
191 }
192 table[Index]=pte;
193 // Update fast lookup table
194 lookupTable.insert(make_pair(table[Index].VPN, Index));
195 }
196}
197
198// insert a new TLB entry
199void
200TLB::insert(Addr addr, PTE &pte)
201{
202 fatal("TLB Insert not yet implemented\n");
203}
204
205void
206TLB::flushAll()
207{
208 DPRINTF(TLB, "flushAll\n");
209 memset(table, 0, sizeof(PTE[size]));
210 lookupTable.clear();
211 nlu = 0;
212}
213
214void
215TLB::serialize(ostream &os)
216{
217 SERIALIZE_SCALAR(size);
218 SERIALIZE_SCALAR(nlu);
219
220 for (int i = 0; i < size; i++) {
221 nameOut(os, csprintf("%s.PTE%d", name(), i));
222 table[i].serialize(os);
223 }
224}
225
226void
227TLB::unserialize(Checkpoint *cp, const string §ion)
228{
229 UNSERIALIZE_SCALAR(size);
230 UNSERIALIZE_SCALAR(nlu);
231
232 for (int i = 0; i < size; i++) {
233 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
234 if (table[i].V0 || table[i].V1) {
235 lookupTable.insert(make_pair(table[i].VPN, i));
236 }
237 }
238}
239
240void
241TLB::regStats()
242{
243 read_hits
244 .name(name() + ".read_hits")
245 .desc("DTB read hits")
246 ;
247
248 read_misses
249 .name(name() + ".read_misses")
250 .desc("DTB read misses")
251 ;
252
253
254 read_accesses
255 .name(name() + ".read_accesses")
256 .desc("DTB read accesses")
257 ;
258
259 write_hits
260 .name(name() + ".write_hits")
261 .desc("DTB write hits")
262 ;
263
264 write_misses
265 .name(name() + ".write_misses")
266 .desc("DTB write misses")
267 ;
268
269
270 write_accesses
271 .name(name() + ".write_accesses")
272 .desc("DTB write accesses")
273 ;
274
275 hits
276 .name(name() + ".hits")
277 .desc("DTB hits")
278 ;
279
280 misses
281 .name(name() + ".misses")
282 .desc("DTB misses")
283 ;
284
285 accesses
286 .name(name() + ".accesses")
287 .desc("DTB accesses")
288 ;
289
290 hits = read_hits + write_hits;
291 misses = read_misses + write_misses;
292 accesses = read_accesses + write_accesses;
293}
294
295Fault
296TLB::translateInst(RequestPtr req, ThreadContext *tc)
297{
298 if (FullSystem)
299 panic("translateInst not implemented in MIPS.\n");
300
301 Process * p = tc->getProcessPtr();
302
303 Fault fault = p->pTable->translate(req);
304 if (fault != NoFault)
305 return fault;
306
307 return NoFault;
308}
309
310Fault
311TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
312{
313 if (FullSystem)
314 panic("translateData not implemented in MIPS.\n");
315
316 Process * p = tc->getProcessPtr();
317
318 Fault fault = p->pTable->translate(req);
319 if (fault != NoFault)
320 return fault;
321
322 return NoFault;
323}
324
325Fault
326TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
327{
328 if (mode == Execute)
329 return translateInst(req, tc);
330 else
331 return translateData(req, tc, mode == Write);
332}
333
334void
335TLB::translateTiming(RequestPtr req, ThreadContext *tc,
336 Translation *translation, Mode mode)
337{
338 assert(translation);
339 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
340}
341
342Fault
343TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
344{
345 panic("Not implemented\n");
346 return NoFault;
347}
348
349Fault
350TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
351{
352 return NoFault;
353}
354
355
356MipsISA::PTE &
357TLB::index(bool advance)
358{
359 PTE *pte = &table[nlu];
360
361 if (advance)
362 nextnlu();
363
364 return *pte;
365}
366
367MipsISA::TLB *
368MipsTLBParams::create()
369{
370 return new TLB(this);
371}
|