tlb.cc (11793:ef606668d247) tlb.cc (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include "arch/mips/tlb.hh"
37
38#include <string>
39#include <vector>
40
41#include "arch/mips/faults.hh"
42#include "arch/mips/pagetable.hh"
43#include "arch/mips/pra_constants.hh"
44#include "arch/mips/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/MipsPRA.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/MipsTLB.hh"
53#include "sim/process.hh"
54
55using namespace std;
56using namespace MipsISA;
57
58///////////////////////////////////////////////////////////////////////
59//
60// MIPS TLB
61//
62
63TLB::TLB(const Params *p)
64 : BaseTLB(p), size(p->size), nlu(0)
65{
66 table = new PTE[size];
67 memset(table, 0, sizeof(PTE[size]));
68 smallPages = 0;
69}
70
71TLB::~TLB()
72{
73 if (table)
74 delete [] table;
75}
76
77// look up an entry in the TLB
78MipsISA::PTE *
79TLB::lookup(Addr vpn, uint8_t asn) const
80{
81 // assume not found...
82 PTE *retval = NULL;
83 PageTable::const_iterator i = lookupTable.find(vpn);
84 if (i != lookupTable.end()) {
85 while (i->first == vpn) {
86 int index = i->second;
87 PTE *pte = &table[index];
88
89 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
90 Addr Mask = pte->Mask;
91 Addr InvMask = ~Mask;
92 Addr VPN = pte->VPN;
93 if (((vpn & InvMask) == (VPN & InvMask)) &&
94 (pte->G || (asn == pte->asid))) {
95 // We have a VPN + ASID Match
96 retval = pte;
97 break;
98 }
99 ++i;
100 }
101 }
102
103 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
104 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
105 return retval;
106}
107
108MipsISA::PTE*
109TLB::getEntry(unsigned Index) const
110{
111 // Make sure that Index is valid
112 assert(Index<size);
113 return &table[Index];
114}
115
116int
117TLB::probeEntry(Addr vpn, uint8_t asn) const
118{
119 // assume not found...
120 int Ind = -1;
121 PageTable::const_iterator i = lookupTable.find(vpn);
122 if (i != lookupTable.end()) {
123 while (i->first == vpn) {
124 int index = i->second;
125 PTE *pte = &table[index];
126
127 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
128 Addr Mask = pte->Mask;
129 Addr InvMask = ~Mask;
130 Addr VPN = pte->VPN;
131 if (((vpn & InvMask) == (VPN & InvMask)) &&
132 (pte->G || (asn == pte->asid))) {
133 // We have a VPN + ASID Match
134 Ind = index;
135 break;
136 }
137 ++i;
138 }
139 }
140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
141 return Ind;
142}
143
144inline Fault
145TLB::checkCacheability(RequestPtr &req)
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual
149 // address or by the TLB entry
150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
153 }
154 return NoFault;
155}
156
157void
158TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
159{
160 smallPages = _smallPages;
161 if (Index > size) {
162 warn("Attempted to write at index (%d) beyond TLB size (%d)",
163 Index, size);
164 } else {
165 // Update TLB
166 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
167 Index, pte.Mask << 11,
168 ((pte.VPN << 11) | pte.asid),
169 ((pte.PFN0 << 6) | (pte.C0 << 3) |
170 (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
171 ((pte.PFN1 <<6) | (pte.C1 << 3) |
172 (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
173 if (table[Index].V0 || table[Index].V1) {
174 // Previous entry is valid
175 PageTable::iterator i = lookupTable.find(table[Index].VPN);
176 lookupTable.erase(i);
177 }
178 table[Index]=pte;
179 // Update fast lookup table
180 lookupTable.insert(make_pair(table[Index].VPN, Index));
181 }
182}
183
184// insert a new TLB entry
185void
186TLB::insert(Addr addr, PTE &pte)
187{
188 fatal("TLB Insert not yet implemented\n");
189}
190
191void
192TLB::flushAll()
193{
194 DPRINTF(TLB, "flushAll\n");
195 memset(table, 0, sizeof(PTE[size]));
196 lookupTable.clear();
197 nlu = 0;
198}
199
200void
201TLB::serialize(CheckpointOut &cp) const
202{
203 SERIALIZE_SCALAR(size);
204 SERIALIZE_SCALAR(nlu);
205
206 for (int i = 0; i < size; i++) {
207 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
208 table[i].serialize(cp);
209 }
210}
211
212void
213TLB::unserialize(CheckpointIn &cp)
214{
215 UNSERIALIZE_SCALAR(size);
216 UNSERIALIZE_SCALAR(nlu);
217
218 for (int i = 0; i < size; i++) {
219 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
220 table[i].unserialize(cp);
221 if (table[i].V0 || table[i].V1) {
222 lookupTable.insert(make_pair(table[i].VPN, i));
223 }
224 }
225}
226
227void
228TLB::regStats()
229{
230 BaseTLB::regStats();
231
232 read_hits
233 .name(name() + ".read_hits")
234 .desc("DTB read hits")
235 ;
236
237 read_misses
238 .name(name() + ".read_misses")
239 .desc("DTB read misses")
240 ;
241
242
243 read_accesses
244 .name(name() + ".read_accesses")
245 .desc("DTB read accesses")
246 ;
247
248 write_hits
249 .name(name() + ".write_hits")
250 .desc("DTB write hits")
251 ;
252
253 write_misses
254 .name(name() + ".write_misses")
255 .desc("DTB write misses")
256 ;
257
258
259 write_accesses
260 .name(name() + ".write_accesses")
261 .desc("DTB write accesses")
262 ;
263
264 hits
265 .name(name() + ".hits")
266 .desc("DTB hits")
267 ;
268
269 misses
270 .name(name() + ".misses")
271 .desc("DTB misses")
272 ;
273
274 accesses
275 .name(name() + ".accesses")
276 .desc("DTB accesses")
277 ;
278
279 hits = read_hits + write_hits;
280 misses = read_misses + write_misses;
281 accesses = read_accesses + write_accesses;
282}
283
284Fault
285TLB::translateInst(RequestPtr req, ThreadContext *tc)
286{
287 if (FullSystem)
288 panic("translateInst not implemented in MIPS.\n");
289
290 Process * p = tc->getProcessPtr();
291
292 Fault fault = p->pTable->translate(req);
293 if (fault != NoFault)
294 return fault;
295
296 return NoFault;
297}
298
299Fault
300TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
301{
302 if (FullSystem)
303 panic("translateData not implemented in MIPS.\n");
304
305 Process * p = tc->getProcessPtr();
306
307 Fault fault = p->pTable->translate(req);
308 if (fault != NoFault)
309 return fault;
310
311 return NoFault;
312}
313
314Fault
315TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
316{
317 if (mode == Execute)
318 return translateInst(req, tc);
319 else
320 return translateData(req, tc, mode == Write);
321}
322
323void
324TLB::translateTiming(RequestPtr req, ThreadContext *tc,
325 Translation *translation, Mode mode)
326{
327 assert(translation);
328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
329}
330
331Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
34 */
35
36#include "arch/mips/tlb.hh"
37
38#include <string>
39#include <vector>
40
41#include "arch/mips/faults.hh"
42#include "arch/mips/pagetable.hh"
43#include "arch/mips/pra_constants.hh"
44#include "arch/mips/utility.hh"
45#include "base/inifile.hh"
46#include "base/str.hh"
47#include "base/trace.hh"
48#include "cpu/thread_context.hh"
49#include "debug/MipsPRA.hh"
50#include "debug/TLB.hh"
51#include "mem/page_table.hh"
52#include "params/MipsTLB.hh"
53#include "sim/process.hh"
54
55using namespace std;
56using namespace MipsISA;
57
58///////////////////////////////////////////////////////////////////////
59//
60// MIPS TLB
61//
62
63TLB::TLB(const Params *p)
64 : BaseTLB(p), size(p->size), nlu(0)
65{
66 table = new PTE[size];
67 memset(table, 0, sizeof(PTE[size]));
68 smallPages = 0;
69}
70
71TLB::~TLB()
72{
73 if (table)
74 delete [] table;
75}
76
77// look up an entry in the TLB
78MipsISA::PTE *
79TLB::lookup(Addr vpn, uint8_t asn) const
80{
81 // assume not found...
82 PTE *retval = NULL;
83 PageTable::const_iterator i = lookupTable.find(vpn);
84 if (i != lookupTable.end()) {
85 while (i->first == vpn) {
86 int index = i->second;
87 PTE *pte = &table[index];
88
89 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
90 Addr Mask = pte->Mask;
91 Addr InvMask = ~Mask;
92 Addr VPN = pte->VPN;
93 if (((vpn & InvMask) == (VPN & InvMask)) &&
94 (pte->G || (asn == pte->asid))) {
95 // We have a VPN + ASID Match
96 retval = pte;
97 break;
98 }
99 ++i;
100 }
101 }
102
103 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
104 retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
105 return retval;
106}
107
108MipsISA::PTE*
109TLB::getEntry(unsigned Index) const
110{
111 // Make sure that Index is valid
112 assert(Index<size);
113 return &table[Index];
114}
115
116int
117TLB::probeEntry(Addr vpn, uint8_t asn) const
118{
119 // assume not found...
120 int Ind = -1;
121 PageTable::const_iterator i = lookupTable.find(vpn);
122 if (i != lookupTable.end()) {
123 while (i->first == vpn) {
124 int index = i->second;
125 PTE *pte = &table[index];
126
127 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
128 Addr Mask = pte->Mask;
129 Addr InvMask = ~Mask;
130 Addr VPN = pte->VPN;
131 if (((vpn & InvMask) == (VPN & InvMask)) &&
132 (pte->G || (asn == pte->asid))) {
133 // We have a VPN + ASID Match
134 Ind = index;
135 break;
136 }
137 ++i;
138 }
139 }
140 DPRINTF(MipsPRA,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
141 return Ind;
142}
143
144inline Fault
145TLB::checkCacheability(RequestPtr &req)
146{
147 Addr VAddrUncacheable = 0xA0000000;
148 // In MIPS, cacheability is controlled by certain bits of the virtual
149 // address or by the TLB entry
150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
151 // mark request as uncacheable
152 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
153 }
154 return NoFault;
155}
156
157void
158TLB::insertAt(PTE &pte, unsigned Index, int _smallPages)
159{
160 smallPages = _smallPages;
161 if (Index > size) {
162 warn("Attempted to write at index (%d) beyond TLB size (%d)",
163 Index, size);
164 } else {
165 // Update TLB
166 DPRINTF(TLB, "TLB[%d]: %x %x %x %x\n",
167 Index, pte.Mask << 11,
168 ((pte.VPN << 11) | pte.asid),
169 ((pte.PFN0 << 6) | (pte.C0 << 3) |
170 (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
171 ((pte.PFN1 <<6) | (pte.C1 << 3) |
172 (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
173 if (table[Index].V0 || table[Index].V1) {
174 // Previous entry is valid
175 PageTable::iterator i = lookupTable.find(table[Index].VPN);
176 lookupTable.erase(i);
177 }
178 table[Index]=pte;
179 // Update fast lookup table
180 lookupTable.insert(make_pair(table[Index].VPN, Index));
181 }
182}
183
184// insert a new TLB entry
185void
186TLB::insert(Addr addr, PTE &pte)
187{
188 fatal("TLB Insert not yet implemented\n");
189}
190
191void
192TLB::flushAll()
193{
194 DPRINTF(TLB, "flushAll\n");
195 memset(table, 0, sizeof(PTE[size]));
196 lookupTable.clear();
197 nlu = 0;
198}
199
200void
201TLB::serialize(CheckpointOut &cp) const
202{
203 SERIALIZE_SCALAR(size);
204 SERIALIZE_SCALAR(nlu);
205
206 for (int i = 0; i < size; i++) {
207 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
208 table[i].serialize(cp);
209 }
210}
211
212void
213TLB::unserialize(CheckpointIn &cp)
214{
215 UNSERIALIZE_SCALAR(size);
216 UNSERIALIZE_SCALAR(nlu);
217
218 for (int i = 0; i < size; i++) {
219 ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
220 table[i].unserialize(cp);
221 if (table[i].V0 || table[i].V1) {
222 lookupTable.insert(make_pair(table[i].VPN, i));
223 }
224 }
225}
226
227void
228TLB::regStats()
229{
230 BaseTLB::regStats();
231
232 read_hits
233 .name(name() + ".read_hits")
234 .desc("DTB read hits")
235 ;
236
237 read_misses
238 .name(name() + ".read_misses")
239 .desc("DTB read misses")
240 ;
241
242
243 read_accesses
244 .name(name() + ".read_accesses")
245 .desc("DTB read accesses")
246 ;
247
248 write_hits
249 .name(name() + ".write_hits")
250 .desc("DTB write hits")
251 ;
252
253 write_misses
254 .name(name() + ".write_misses")
255 .desc("DTB write misses")
256 ;
257
258
259 write_accesses
260 .name(name() + ".write_accesses")
261 .desc("DTB write accesses")
262 ;
263
264 hits
265 .name(name() + ".hits")
266 .desc("DTB hits")
267 ;
268
269 misses
270 .name(name() + ".misses")
271 .desc("DTB misses")
272 ;
273
274 accesses
275 .name(name() + ".accesses")
276 .desc("DTB accesses")
277 ;
278
279 hits = read_hits + write_hits;
280 misses = read_misses + write_misses;
281 accesses = read_accesses + write_accesses;
282}
283
284Fault
285TLB::translateInst(RequestPtr req, ThreadContext *tc)
286{
287 if (FullSystem)
288 panic("translateInst not implemented in MIPS.\n");
289
290 Process * p = tc->getProcessPtr();
291
292 Fault fault = p->pTable->translate(req);
293 if (fault != NoFault)
294 return fault;
295
296 return NoFault;
297}
298
299Fault
300TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
301{
302 if (FullSystem)
303 panic("translateData not implemented in MIPS.\n");
304
305 Process * p = tc->getProcessPtr();
306
307 Fault fault = p->pTable->translate(req);
308 if (fault != NoFault)
309 return fault;
310
311 return NoFault;
312}
313
314Fault
315TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
316{
317 if (mode == Execute)
318 return translateInst(req, tc);
319 else
320 return translateData(req, tc, mode == Write);
321}
322
323void
324TLB::translateTiming(RequestPtr req, ThreadContext *tc,
325 Translation *translation, Mode mode)
326{
327 assert(translation);
328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
329}
330
331Fault
332TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
333{
334 panic("Not implemented\n");
335 return NoFault;
336}
337
338Fault
339TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
340{
341 return NoFault;
342}
343
344
345MipsISA::PTE &
346TLB::index(bool advance)
347{
348 PTE *pte = &table[nlu];
349
350 if (advance)
351 nextnlu();
352
353 return *pte;
354}
355
356MipsISA::TLB *
357MipsTLBParams::create()
358{
359 return new TLB(this);
360}
332TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
333{
334 return NoFault;
335}
336
337
338MipsISA::PTE &
339TLB::index(bool advance)
340{
341 PTE *pte = &table[nlu];
342
343 if (advance)
344 nextnlu();
345
346 return *pte;
347}
348
349MipsISA::TLB *
350MipsTLBParams::create()
351{
352 return new TLB(this);
353}