1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#include <string>
32
33#include "arch/mips/isa_traits.hh"
34#include "arch/mips/stacktrace.hh"
35#include "arch/mips/vtophys.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/base.hh"
39#include "cpu/thread_context.hh"
40#include "mem/vport.hh"
41#include "sim/system.hh"
42
43using namespace std;
44using namespace MipsISA;
45
46ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
47{}
48
49Addr
50ProcessInfo::task(Addr ksp) const
51{
52 Addr base = ksp & ~0x3fff;
53 if (base == ULL(0xfffffc0000000000))
54 return 0;
55
56 Addr tsk;
57
57 FSTranslatingPortProxy* vp;
58 VirtualPort *vp;
59
59 vp = tc->getVirtProxy();
60 vp = tc->getVirtPort();
61 tsk = vp->readGtoH<Addr>(base + task_off);
62
63 return tsk;
64}
65
66int
67ProcessInfo::pid(Addr ksp) const
68{
69 Addr task = this->task(ksp);
70 if (!task)
71 return -1;
72
73 uint16_t pd;
74
74 FSTranslatingPortProxy* vp;
75 VirtualPort *vp;
76
76 vp = tc->getVirtProxy();
77 vp = tc->getVirtPort();
78 pd = vp->readGtoH<uint16_t>(task + pid_off);
79
80 return pd;
81}
82
83string
84ProcessInfo::name(Addr ksp) const
85{
86 Addr task = this->task(ksp);
87 if (!task)
88 return "console";
89
90 char comm[256];
91 CopyStringOut(tc, comm, task + name_off, sizeof(comm));
92 if (!comm[0])
93 return "startup";
94
95 return comm;
96}
97
98StackTrace::StackTrace()
99 : tc(0), stack(64)
100{
101}
102
103StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
104 : tc(0), stack(64)
105{
106 trace(_tc, inst);
107}
108
109StackTrace::~StackTrace()
110{
111}
112
113void
114StackTrace::trace(ThreadContext *_tc, bool is_call)
115{
116 tc = _tc;
117 bool usermode = 0;
118
119 if (usermode) {
120 stack.push_back(user);
121 return;
122 }
123}
124
125bool
126StackTrace::isEntry(Addr addr)
127{
128 return false;
129}
130
131bool
132StackTrace::decodeStack(MachInst inst, int &disp)
133{
134 // lda $sp, -disp($sp)
135 //
136 // Opcode<31:26> == 0x08
137 // RA<25:21> == 30
138 // RB<20:16> == 30
139 // Disp<15:0>
140 const MachInst mem_mask = 0xffff0000;
141 const MachInst lda_pattern = 0x23de0000;
142 const MachInst lda_disp_mask = 0x0000ffff;
143
144 // subq $sp, disp, $sp
145 // addq $sp, disp, $sp
146 //
147 // Opcode<31:26> == 0x10
148 // RA<25:21> == 30
149 // Lit<20:13>
150 // One<12> = 1
151 // Func<11:5> == 0x20 (addq)
152 // Func<11:5> == 0x29 (subq)
153 // RC<4:0> == 30
154 const MachInst intop_mask = 0xffe01fff;
155 const MachInst addq_pattern = 0x43c0141e;
156 const MachInst subq_pattern = 0x43c0153e;
157 const MachInst intop_disp_mask = 0x001fe000;
158 const int intop_disp_shift = 13;
159
160 if ((inst & mem_mask) == lda_pattern)
161 disp = -sext<16>(inst & lda_disp_mask);
162 else if ((inst & intop_mask) == addq_pattern)
163 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
164 else if ((inst & intop_mask) == subq_pattern)
165 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
166 else
167 return false;
168
169 return true;
170}
171
172bool
173StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
174{
175 // lda $stq, disp($sp)
176 //
177 // Opcode<31:26> == 0x08
178 // RA<25:21> == ?
179 // RB<20:16> == 30
180 // Disp<15:0>
181 const MachInst stq_mask = 0xfc1f0000;
182 const MachInst stq_pattern = 0xb41e0000;
183 const MachInst stq_disp_mask = 0x0000ffff;
184 const MachInst reg_mask = 0x03e00000;
185 const int reg_shift = 21;
186
187 if ((inst & stq_mask) == stq_pattern) {
188 reg = (inst & reg_mask) >> reg_shift;
189 disp = sext<16>(inst & stq_disp_mask);
190 } else {
191 return false;
192 }
193
194 return true;
195}
196
197/*
198 * Decode the function prologue for the function we're in, and note
199 * which registers are stored where, and how large the stack frame is.
200 */
201bool
202StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
203 int &size, Addr &ra)
204{
205 size = 0;
206 ra = 0;
207
208 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
209 MachInst inst;
210 CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
211
212 int reg, disp;
213 if (decodeStack(inst, disp)) {
214 if (size) {
215 return true;
216 }
217 size += disp;
218 } else if (decodeSave(inst, reg, disp)) {
219 if (!ra && reg == ReturnAddressReg) {
220 CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
221 if (!ra) {
222 return false;
223 }
224 }
225 }
226 }
227
228 return true;
229}
230
231#if TRACING_ON
232void
233StackTrace::dump()
234{
235 panic("Stack trace dump not implemented.\n");
236}
237#endif