1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#include <string>
32
33#include "arch/mips/isa_traits.hh"
34#include "arch/mips/stacktrace.hh"
35#include "arch/mips/vtophys.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/base.hh"
39#include "cpu/thread_context.hh"
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#include <string>
32
33#include "arch/mips/isa_traits.hh"
34#include "arch/mips/stacktrace.hh"
35#include "arch/mips/vtophys.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/base.hh"
39#include "cpu/thread_context.hh"
|
| 40#include "mem/vport.hh"
|
40#include "sim/system.hh"
41
42using namespace std;
43using namespace MipsISA;
44
45ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
46{}
47
48Addr
49ProcessInfo::task(Addr ksp) const
50{
51 Addr base = ksp & ~0x3fff;
52 if (base == ULL(0xfffffc0000000000))
53 return 0;
54
55 Addr tsk;
56
| 41#include "sim/system.hh"
42
43using namespace std;
44using namespace MipsISA;
45
46ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
47{}
48
49Addr
50ProcessInfo::task(Addr ksp) const
51{
52 Addr base = ksp & ~0x3fff;
53 if (base == ULL(0xfffffc0000000000))
54 return 0;
55
56 Addr tsk;
57
|
57 FSTranslatingPortProxy* vp;
| 58 VirtualPort *vp;
|
58
| 59
|
59 vp = tc->getVirtProxy();
| 60 vp = tc->getVirtPort();
|
60 tsk = vp->readGtoH<Addr>(base + task_off);
61
62 return tsk;
63}
64
65int
66ProcessInfo::pid(Addr ksp) const
67{
68 Addr task = this->task(ksp);
69 if (!task)
70 return -1;
71
72 uint16_t pd;
73
| 61 tsk = vp->readGtoH<Addr>(base + task_off);
62
63 return tsk;
64}
65
66int
67ProcessInfo::pid(Addr ksp) const
68{
69 Addr task = this->task(ksp);
70 if (!task)
71 return -1;
72
73 uint16_t pd;
74
|
74 FSTranslatingPortProxy* vp;
| 75 VirtualPort *vp;
|
75
| 76
|
76 vp = tc->getVirtProxy();
| 77 vp = tc->getVirtPort();
|
77 pd = vp->readGtoH<uint16_t>(task + pid_off);
78
79 return pd;
80}
81
82string
83ProcessInfo::name(Addr ksp) const
84{
85 Addr task = this->task(ksp);
86 if (!task)
87 return "console";
88
89 char comm[256];
90 CopyStringOut(tc, comm, task + name_off, sizeof(comm));
91 if (!comm[0])
92 return "startup";
93
94 return comm;
95}
96
97StackTrace::StackTrace()
98 : tc(0), stack(64)
99{
100}
101
102StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
103 : tc(0), stack(64)
104{
105 trace(_tc, inst);
106}
107
108StackTrace::~StackTrace()
109{
110}
111
112void
113StackTrace::trace(ThreadContext *_tc, bool is_call)
114{
115 tc = _tc;
116 bool usermode = 0;
117
118 if (usermode) {
119 stack.push_back(user);
120 return;
121 }
122}
123
124bool
125StackTrace::isEntry(Addr addr)
126{
127 return false;
128}
129
130bool
131StackTrace::decodeStack(MachInst inst, int &disp)
132{
133 // lda $sp, -disp($sp)
134 //
135 // Opcode<31:26> == 0x08
136 // RA<25:21> == 30
137 // RB<20:16> == 30
138 // Disp<15:0>
139 const MachInst mem_mask = 0xffff0000;
140 const MachInst lda_pattern = 0x23de0000;
141 const MachInst lda_disp_mask = 0x0000ffff;
142
143 // subq $sp, disp, $sp
144 // addq $sp, disp, $sp
145 //
146 // Opcode<31:26> == 0x10
147 // RA<25:21> == 30
148 // Lit<20:13>
149 // One<12> = 1
150 // Func<11:5> == 0x20 (addq)
151 // Func<11:5> == 0x29 (subq)
152 // RC<4:0> == 30
153 const MachInst intop_mask = 0xffe01fff;
154 const MachInst addq_pattern = 0x43c0141e;
155 const MachInst subq_pattern = 0x43c0153e;
156 const MachInst intop_disp_mask = 0x001fe000;
157 const int intop_disp_shift = 13;
158
159 if ((inst & mem_mask) == lda_pattern)
160 disp = -sext<16>(inst & lda_disp_mask);
161 else if ((inst & intop_mask) == addq_pattern)
162 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
163 else if ((inst & intop_mask) == subq_pattern)
164 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
165 else
166 return false;
167
168 return true;
169}
170
171bool
172StackTrace::decodeSave(MachInst inst, int ®, int &disp)
173{
174 // lda $stq, disp($sp)
175 //
176 // Opcode<31:26> == 0x08
177 // RA<25:21> == ?
178 // RB<20:16> == 30
179 // Disp<15:0>
180 const MachInst stq_mask = 0xfc1f0000;
181 const MachInst stq_pattern = 0xb41e0000;
182 const MachInst stq_disp_mask = 0x0000ffff;
183 const MachInst reg_mask = 0x03e00000;
184 const int reg_shift = 21;
185
186 if ((inst & stq_mask) == stq_pattern) {
187 reg = (inst & reg_mask) >> reg_shift;
188 disp = sext<16>(inst & stq_disp_mask);
189 } else {
190 return false;
191 }
192
193 return true;
194}
195
196/*
197 * Decode the function prologue for the function we're in, and note
198 * which registers are stored where, and how large the stack frame is.
199 */
200bool
201StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
202 int &size, Addr &ra)
203{
204 size = 0;
205 ra = 0;
206
207 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
208 MachInst inst;
209 CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
210
211 int reg, disp;
212 if (decodeStack(inst, disp)) {
213 if (size) {
214 return true;
215 }
216 size += disp;
217 } else if (decodeSave(inst, reg, disp)) {
218 if (!ra && reg == ReturnAddressReg) {
219 CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
220 if (!ra) {
221 return false;
222 }
223 }
224 }
225 }
226
227 return true;
228}
229
230#if TRACING_ON
231void
232StackTrace::dump()
233{
234 panic("Stack trace dump not implemented.\n");
235}
236#endif
| 78 pd = vp->readGtoH<uint16_t>(task + pid_off);
79
80 return pd;
81}
82
83string
84ProcessInfo::name(Addr ksp) const
85{
86 Addr task = this->task(ksp);
87 if (!task)
88 return "console";
89
90 char comm[256];
91 CopyStringOut(tc, comm, task + name_off, sizeof(comm));
92 if (!comm[0])
93 return "startup";
94
95 return comm;
96}
97
98StackTrace::StackTrace()
99 : tc(0), stack(64)
100{
101}
102
103StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
104 : tc(0), stack(64)
105{
106 trace(_tc, inst);
107}
108
109StackTrace::~StackTrace()
110{
111}
112
113void
114StackTrace::trace(ThreadContext *_tc, bool is_call)
115{
116 tc = _tc;
117 bool usermode = 0;
118
119 if (usermode) {
120 stack.push_back(user);
121 return;
122 }
123}
124
125bool
126StackTrace::isEntry(Addr addr)
127{
128 return false;
129}
130
131bool
132StackTrace::decodeStack(MachInst inst, int &disp)
133{
134 // lda $sp, -disp($sp)
135 //
136 // Opcode<31:26> == 0x08
137 // RA<25:21> == 30
138 // RB<20:16> == 30
139 // Disp<15:0>
140 const MachInst mem_mask = 0xffff0000;
141 const MachInst lda_pattern = 0x23de0000;
142 const MachInst lda_disp_mask = 0x0000ffff;
143
144 // subq $sp, disp, $sp
145 // addq $sp, disp, $sp
146 //
147 // Opcode<31:26> == 0x10
148 // RA<25:21> == 30
149 // Lit<20:13>
150 // One<12> = 1
151 // Func<11:5> == 0x20 (addq)
152 // Func<11:5> == 0x29 (subq)
153 // RC<4:0> == 30
154 const MachInst intop_mask = 0xffe01fff;
155 const MachInst addq_pattern = 0x43c0141e;
156 const MachInst subq_pattern = 0x43c0153e;
157 const MachInst intop_disp_mask = 0x001fe000;
158 const int intop_disp_shift = 13;
159
160 if ((inst & mem_mask) == lda_pattern)
161 disp = -sext<16>(inst & lda_disp_mask);
162 else if ((inst & intop_mask) == addq_pattern)
163 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
164 else if ((inst & intop_mask) == subq_pattern)
165 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
166 else
167 return false;
168
169 return true;
170}
171
172bool
173StackTrace::decodeSave(MachInst inst, int ®, int &disp)
174{
175 // lda $stq, disp($sp)
176 //
177 // Opcode<31:26> == 0x08
178 // RA<25:21> == ?
179 // RB<20:16> == 30
180 // Disp<15:0>
181 const MachInst stq_mask = 0xfc1f0000;
182 const MachInst stq_pattern = 0xb41e0000;
183 const MachInst stq_disp_mask = 0x0000ffff;
184 const MachInst reg_mask = 0x03e00000;
185 const int reg_shift = 21;
186
187 if ((inst & stq_mask) == stq_pattern) {
188 reg = (inst & reg_mask) >> reg_shift;
189 disp = sext<16>(inst & stq_disp_mask);
190 } else {
191 return false;
192 }
193
194 return true;
195}
196
197/*
198 * Decode the function prologue for the function we're in, and note
199 * which registers are stored where, and how large the stack frame is.
200 */
201bool
202StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
203 int &size, Addr &ra)
204{
205 size = 0;
206 ra = 0;
207
208 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
209 MachInst inst;
210 CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
211
212 int reg, disp;
213 if (decodeStack(inst, disp)) {
214 if (size) {
215 return true;
216 }
217 size += disp;
218 } else if (decodeSave(inst, reg, disp)) {
219 if (!ra && reg == ReturnAddressReg) {
220 CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
221 if (!ra) {
222 return false;
223 }
224 }
225 }
226 }
227
228 return true;
229}
230
231#if TRACING_ON
232void
233StackTrace::dump()
234{
235 panic("Stack trace dump not implemented.\n");
236}
237#endif
|