registers.hh (9920:028e4da64b42) | registers.hh (10934:5af8f40d8f2c) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 41 unchanged lines hidden (view full) --- 50const int NumIntSpecialRegs = 9; 51const int NumFloatArchRegs = 32; 52const int NumFloatSpecialRegs = 5; 53 54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 57const int NumCCRegs = 0; | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 41 unchanged lines hidden (view full) --- 50const int NumIntSpecialRegs = 9; 51const int NumFloatArchRegs = 32; 52const int NumFloatSpecialRegs = 5; 53 54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 57const int NumCCRegs = 0; |
58const int NumVectorRegs = 0; |
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58 59const uint32_t MIPS32_QNAN = 0x7fbfffff; 60const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 61 62enum FPControlRegNums { 63 FLOATREG_FIR = NumFloatArchRegs, 64 FLOATREG_FCCR, 65 FLOATREG_FEXR, --- 207 unchanged lines hidden (view full) --- 273 MISCREG_NUMREGS 274}; 275 276const int NumMiscRegs = MISCREG_NUMREGS; 277 278// These help enumerate all the registers for dependence tracking. 279const int FP_Reg_Base = NumIntRegs; 280const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; | 59 60const uint32_t MIPS32_QNAN = 0x7fbfffff; 61const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 62 63enum FPControlRegNums { 64 FLOATREG_FIR = NumFloatArchRegs, 65 FLOATREG_FCCR, 66 FLOATREG_FEXR, --- 207 unchanged lines hidden (view full) --- 274 MISCREG_NUMREGS 275}; 276 277const int NumMiscRegs = MISCREG_NUMREGS; 278 279// These help enumerate all the registers for dependence tracking. 280const int FP_Reg_Base = NumIntRegs; 281const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; |
281const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 | 282const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 283const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; |
282const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 283 284const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 285 286typedef uint16_t RegIndex; 287 288typedef uint32_t IntReg; 289 290// floating point register file entry type 291typedef uint32_t FloatRegBits; 292typedef float FloatReg; 293 294// cop-0/cop-1 system control register 295typedef uint64_t MiscReg; 296 297// dummy typedef since we don't have CC regs 298typedef uint8_t CCReg; 299 | 284const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 285 286const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 287 288typedef uint16_t RegIndex; 289 290typedef uint32_t IntReg; 291 292// floating point register file entry type 293typedef uint32_t FloatRegBits; 294typedef float FloatReg; 295 296// cop-0/cop-1 system control register 297typedef uint64_t MiscReg; 298 299// dummy typedef since we don't have CC regs 300typedef uint8_t CCReg; 301 |
302// vector register file entry type 303typedef uint64_t VectorRegElement; 304const int NumVectorRegElements = 0; 305const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement); 306typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg; 307 |
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300typedef union { 301 IntReg intreg; 302 FloatReg fpreg; 303 MiscReg ctrlreg; 304} AnyReg; 305 306} // namespace MipsISA 307 308#endif | 308typedef union { 309 IntReg intreg; 310 FloatReg fpreg; 311 MiscReg ctrlreg; 312} AnyReg; 313 314} // namespace MipsISA 315 316#endif |