registers.hh (9918:2c7219e2d999) | registers.hh (9920:028e4da64b42) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 40 unchanged lines hidden (view full) --- 49const int NumIntArchRegs = 32; 50const int NumIntSpecialRegs = 9; 51const int NumFloatArchRegs = 32; 52const int NumFloatSpecialRegs = 5; 53 54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 40 unchanged lines hidden (view full) --- 49const int NumIntArchRegs = 32; 50const int NumIntSpecialRegs = 9; 51const int NumFloatArchRegs = 32; 52const int NumFloatSpecialRegs = 5; 53 54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// |
57const int NumCCRegs = 0; |
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57 58const uint32_t MIPS32_QNAN = 0x7fbfffff; 59const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 60 61enum FPControlRegNums { 62 FLOATREG_FIR = NumFloatArchRegs, 63 FLOATREG_FCCR, 64 FLOATREG_FEXR, --- 206 unchanged lines hidden (view full) --- 271 272 MISCREG_NUMREGS 273}; 274 275const int NumMiscRegs = MISCREG_NUMREGS; 276 277// These help enumerate all the registers for dependence tracking. 278const int FP_Reg_Base = NumIntRegs; | 58 59const uint32_t MIPS32_QNAN = 0x7fbfffff; 60const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 61 62enum FPControlRegNums { 63 FLOATREG_FIR = NumFloatArchRegs, 64 FLOATREG_FCCR, 65 FLOATREG_FEXR, --- 206 unchanged lines hidden (view full) --- 272 273 MISCREG_NUMREGS 274}; 275 276const int NumMiscRegs = MISCREG_NUMREGS; 277 278// These help enumerate all the registers for dependence tracking. 279const int FP_Reg_Base = NumIntRegs; |
279const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs; | 280const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 281const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 |
280const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 281 282const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 283 284typedef uint16_t RegIndex; 285 286typedef uint32_t IntReg; 287 288// floating point register file entry type 289typedef uint32_t FloatRegBits; 290typedef float FloatReg; 291 292// cop-0/cop-1 system control register 293typedef uint64_t MiscReg; 294 | 282const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 283 284const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 285 286typedef uint16_t RegIndex; 287 288typedef uint32_t IntReg; 289 290// floating point register file entry type 291typedef uint32_t FloatRegBits; 292typedef float FloatReg; 293 294// cop-0/cop-1 system control register 295typedef uint64_t MiscReg; 296 |
297// dummy typedef since we don't have CC regs 298typedef uint8_t CCReg; 299 |
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295typedef union { 296 IntReg intreg; 297 FloatReg fpreg; 298 MiscReg ctrlreg; 299} AnyReg; 300 301} // namespace MipsISA 302 303#endif | 300typedef union { 301 IntReg intreg; 302 FloatReg fpreg; 303 MiscReg ctrlreg; 304} AnyReg; 305 306} // namespace MipsISA 307 308#endif |