registers.hh (9046:a1104cc13db2) registers.hh (9917:7274310be1bb)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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110const int KernelReg1 = 27;
111const int GlobalPointerReg = 28;
112const int StackPointerReg = 29;
113const int FramePointerReg = 30;
114const int ReturnAddressReg = 31;
115
116const int SyscallPseudoReturnReg = 3;
117
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 101 unchanged lines hidden (view full) ---

110const int KernelReg1 = 27;
111const int GlobalPointerReg = 28;
112const int StackPointerReg = 29;
113const int FramePointerReg = 30;
114const int ReturnAddressReg = 31;
115
116const int SyscallPseudoReturnReg = 3;
117
118//@TODO: Implementing ShadowSets needs to
119//edit this value such that:
120//TotalArchRegs = NumIntArchRegs * ShadowSets
121const int TotalArchRegs = NumIntArchRegs;
122
123// These help enumerate all the registers for dependence tracking.
124const int FP_Base_DepTag = NumIntRegs;
125const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
126
127// Enumerate names for 'Control' Registers in the CPU
128// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
129// (Register Number-Register Select) Summary of Register
130//------------------------------------------------------
131// The first set of names classify the CP0 names as Register Banks
132// for easy indexing when using the 'RD + SEL' index combination
133// in CP0 instructions.
134enum MiscRegIndex{

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276 MISCREG_DESAVE = 248, //Bank 31: 248-256
277
278 MISCREG_LLFLAG = 257,
279 MISCREG_TP_VALUE,
280
281 MISCREG_NUMREGS
282};
283
118// Enumerate names for 'Control' Registers in the CPU
119// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
120// (Register Number-Register Select) Summary of Register
121//------------------------------------------------------
122// The first set of names classify the CP0 names as Register Banks
123// for easy indexing when using the 'RD + SEL' index combination
124// in CP0 instructions.
125enum MiscRegIndex{

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267 MISCREG_DESAVE = 248, //Bank 31: 248-256
268
269 MISCREG_LLFLAG = 257,
270 MISCREG_TP_VALUE,
271
272 MISCREG_NUMREGS
273};
274
284const int TotalDataRegs = NumIntRegs + NumFloatRegs;
285
286const int NumMiscRegs = MISCREG_NUMREGS;
275const int NumMiscRegs = MISCREG_NUMREGS;
276
277// These help enumerate all the registers for dependence tracking.
278const int FP_Base_DepTag = NumIntRegs;
279const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
287const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
288
289const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
290
291typedef uint16_t RegIndex;
292
293typedef uint32_t IntReg;
294

--- 16 unchanged lines hidden --- 		280const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs;
281
282const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
283
284typedef uint16_t RegIndex;
285
286typedef uint32_t IntReg;
287

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