registers.hh (7649:a6a6177a5ffa) registers.hh (8694:4f8d7d9c9f15)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
54const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
55const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
56
57const uint32_t MIPS32_QNAN = 0x7fbfffff;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 41 unchanged lines hidden (view full) ---

50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
54const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
55const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
56
57const uint32_t MIPS32_QNAN = 0x7fbfffff;
58const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
58const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
59
60enum FPControlRegNums {
61 FLOATREG_FIR = NumFloatArchRegs,
62 FLOATREG_FCCR,
63 FLOATREG_FEXR,
64 FLOATREG_FENR,
65 FLOATREG_FCSR
66};

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60enum FPControlRegNums {
61 FLOATREG_FIR = NumFloatArchRegs,
62 FLOATREG_FCCR,
63 FLOATREG_FEXR,
64 FLOATREG_FENR,
65 FLOATREG_FCSR
66};

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