registers.hh (13592:b8972ccebd63) | registers.hh (13610:5d5404ac6288) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_REGISTERS_HH__ 33#define __ARCH_MIPS_REGISTERS_HH__ 34 | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_REGISTERS_HH__ 33#define __ARCH_MIPS_REGISTERS_HH__ 34 |
35#include "arch/generic/vec_pred_reg.hh" |
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35#include "arch/generic/vec_reg.hh" 36#include "arch/mips/generated/max_inst_regs.hh" 37#include "base/logging.hh" 38#include "base/types.hh" 39 40class ThreadContext; 41 42namespace MipsISA --- 7 unchanged lines hidden (view full) --- 50const int NumIntArchRegs = 32; 51const int NumIntSpecialRegs = 9; 52const int NumFloatArchRegs = 32; 53const int NumFloatSpecialRegs = 5; 54 55const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 56const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 57const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// | 36#include "arch/generic/vec_reg.hh" 37#include "arch/mips/generated/max_inst_regs.hh" 38#include "base/logging.hh" 39#include "base/types.hh" 40 41class ThreadContext; 42 43namespace MipsISA --- 7 unchanged lines hidden (view full) --- 51const int NumIntArchRegs = 32; 52const int NumIntSpecialRegs = 9; 53const int NumFloatArchRegs = 32; 54const int NumFloatSpecialRegs = 5; 55 56const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 57const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 58const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// |
59const int NumVecRegs = 1; // Not applicable to MIPS 60 // (1 to prevent warnings) 61const int NumVecPredRegs = 1; // Not applicable to MIPS 62 // (1 to prevent warnings) |
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58const int NumCCRegs = 0; 59 60const uint32_t MIPS32_QNAN = 0x7fbfffff; 61const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 62 63enum FPControlRegNums { 64 FLOATREG_FIR = NumFloatArchRegs, 65 FLOATREG_FCCR, --- 218 unchanged lines hidden (view full) --- 284typedef RegVal FloatRegBits; 285 286// cop-0/cop-1 system control register 287typedef RegVal MiscReg; 288 289// dummy typedef since we don't have CC regs 290typedef uint8_t CCReg; 291 | 63const int NumCCRegs = 0; 64 65const uint32_t MIPS32_QNAN = 0x7fbfffff; 66const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 67 68enum FPControlRegNums { 69 FLOATREG_FIR = NumFloatArchRegs, 70 FLOATREG_FCCR, --- 218 unchanged lines hidden (view full) --- 289typedef RegVal FloatRegBits; 290 291// cop-0/cop-1 system control register 292typedef RegVal MiscReg; 293 294// dummy typedef since we don't have CC regs 295typedef uint8_t CCReg; 296 |
292// dummy typedefs since we don't have vector regs 293constexpr unsigned NumVecElemPerVecReg = 2; 294using VecElem = uint32_t; 295using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 296using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 297using VecRegContainer = VecReg::Container; 298// This has to be one to prevent warnings that are treated as errors 299constexpr unsigned NumVecRegs = 1; | 297// Not applicable to MIPS 298using VecElem = ::DummyVecElem; 299using VecReg = ::DummyVecReg; 300using ConstVecReg = ::DummyConstVecReg; 301using VecRegContainer = ::DummyVecRegContainer; 302constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 303constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; |
300 | 304 |
305// Not applicable to MIPS 306using VecPredReg = ::DummyVecPredReg; 307using ConstVecPredReg = ::DummyConstVecPredReg; 308using VecPredRegContainer = ::DummyVecPredRegContainer; 309constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 310constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 311 |
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301} // namespace MipsISA 302 303#endif | 312} // namespace MipsISA 313 314#endif |