registers.hh (9918:2c7219e2d999) registers.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/generated/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46using MipsISAInst::MaxMiscDestRegs;
47
48// Constants Related to the number of registers
49const int NumIntArchRegs = 32;
50const int NumIntSpecialRegs = 9;
51const int NumFloatArchRegs = 32;
52const int NumFloatSpecialRegs = 5;
53
54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/generated/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46using MipsISAInst::MaxMiscDestRegs;
47
48// Constants Related to the number of registers
49const int NumIntArchRegs = 32;
50const int NumIntSpecialRegs = 9;
51const int NumFloatArchRegs = 32;
52const int NumFloatSpecialRegs = 5;
53
54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
57const int NumCCRegs = 0;
57
58const uint32_t MIPS32_QNAN = 0x7fbfffff;
59const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
60
61enum FPControlRegNums {
62 FLOATREG_FIR = NumFloatArchRegs,
63 FLOATREG_FCCR,
64 FLOATREG_FEXR,
65 FLOATREG_FENR,
66 FLOATREG_FCSR
67};
68
69enum FCSRBits {
70 Inexact = 1,
71 Underflow,
72 Overflow,
73 DivideByZero,
74 Invalid,
75 Unimplemented
76};
77
78enum FCSRFields {
79 Flag_Field = 1,
80 Enable_Field = 6,
81 Cause_Field = 11
82};
83
84enum MiscIntRegNums {
85 INTREG_LO = NumIntArchRegs,
86 INTREG_DSP_LO0 = INTREG_LO,
87 INTREG_HI,
88 INTREG_DSP_HI0 = INTREG_HI,
89 INTREG_DSP_ACX0,
90 INTREG_DSP_LO1,
91 INTREG_DSP_HI1,
92 INTREG_DSP_ACX1,
93 INTREG_DSP_LO2,
94 INTREG_DSP_HI2,
95 INTREG_DSP_ACX2,
96 INTREG_DSP_LO3,
97 INTREG_DSP_HI3,
98 INTREG_DSP_ACX3,
99 INTREG_DSP_CONTROL
100};
101
102// semantically meaningful register indices
103const int ZeroReg = 0;
104const int AssemblerReg = 1;
105const int SyscallSuccessReg = 7;
106const int FirstArgumentReg = 4;
107const int ReturnValueReg = 2;
108
109const int KernelReg0 = 26;
110const int KernelReg1 = 27;
111const int GlobalPointerReg = 28;
112const int StackPointerReg = 29;
113const int FramePointerReg = 30;
114const int ReturnAddressReg = 31;
115
116const int SyscallPseudoReturnReg = 3;
117
118// Enumerate names for 'Control' Registers in the CPU
119// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
120// (Register Number-Register Select) Summary of Register
121//------------------------------------------------------
122// The first set of names classify the CP0 names as Register Banks
123// for easy indexing when using the 'RD + SEL' index combination
124// in CP0 instructions.
125enum MiscRegIndex{
126 MISCREG_INDEX = 0, //Bank 0: 0 - 3
127 MISCREG_MVP_CONTROL,
128 MISCREG_MVP_CONF0,
129 MISCREG_MVP_CONF1,
130
131 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
132 MISCREG_VPE_CONTROL,
133 MISCREG_VPE_CONF0,
134 MISCREG_VPE_CONF1,
135 MISCREG_YQMASK,
136 MISCREG_VPE_SCHEDULE,
137 MISCREG_VPE_SCHEFBACK,
138 MISCREG_VPE_OPT,
139
140 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
141 MISCREG_TC_STATUS,
142 MISCREG_TC_BIND,
143 MISCREG_TC_RESTART,
144 MISCREG_TC_HALT,
145 MISCREG_TC_CONTEXT,
146 MISCREG_TC_SCHEDULE,
147 MISCREG_TC_SCHEFBACK,
148
149 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
150
151 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
152 MISCREG_CONTEXT_CONFIG,
153
154 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
155 MISCREG_PAGEGRAIN = 41,
156
157 MISCREG_WIRED = 48, //Bank 6:48-55
158 MISCREG_SRS_CONF0,
159 MISCREG_SRS_CONF1,
160 MISCREG_SRS_CONF2,
161 MISCREG_SRS_CONF3,
162 MISCREG_SRS_CONF4,
163
164 MISCREG_HWRENA = 56, //Bank 7: 56-63
165
166 MISCREG_BADVADDR = 64, //Bank 8: 64-71
167
168 MISCREG_COUNT = 72, //Bank 9: 72-79
169
170 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
171
172 MISCREG_COMPARE = 88, //Bank 11: 88-95
173
174 MISCREG_STATUS = 96, //Bank 12: 96-103
175 MISCREG_INTCTL,
176 MISCREG_SRSCTL,
177 MISCREG_SRSMAP,
178
179 MISCREG_CAUSE = 104, //Bank 13: 104-111
180
181 MISCREG_EPC = 112, //Bank 14: 112-119
182
183 MISCREG_PRID = 120, //Bank 15: 120-127,
184 MISCREG_EBASE,
185
186 MISCREG_CONFIG = 128, //Bank 16: 128-135
187 MISCREG_CONFIG1,
188 MISCREG_CONFIG2,
189 MISCREG_CONFIG3,
190 MISCREG_CONFIG4,
191 MISCREG_CONFIG5,
192 MISCREG_CONFIG6,
193 MISCREG_CONFIG7,
194
195
196 MISCREG_LLADDR = 136, //Bank 17: 136-143
197
198 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
199 MISCREG_WATCHLO1,
200 MISCREG_WATCHLO2,
201 MISCREG_WATCHLO3,
202 MISCREG_WATCHLO4,
203 MISCREG_WATCHLO5,
204 MISCREG_WATCHLO6,
205 MISCREG_WATCHLO7,
206
207 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
208 MISCREG_WATCHHI1,
209 MISCREG_WATCHHI2,
210 MISCREG_WATCHHI3,
211 MISCREG_WATCHHI4,
212 MISCREG_WATCHHI5,
213 MISCREG_WATCHHI6,
214 MISCREG_WATCHHI7,
215
216 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
217
218 //Bank 21: 168-175
219
220 //Bank 22: 176-183
221
222 MISCREG_DEBUG = 184, //Bank 23: 184-191
223 MISCREG_TRACE_CONTROL1,
224 MISCREG_TRACE_CONTROL2,
225 MISCREG_USER_TRACE_DATA,
226 MISCREG_TRACE_BPC,
227
228 MISCREG_DEPC = 192, //Bank 24: 192-199
229
230 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
231 MISCREG_PERFCNT1,
232 MISCREG_PERFCNT2,
233 MISCREG_PERFCNT3,
234 MISCREG_PERFCNT4,
235 MISCREG_PERFCNT5,
236 MISCREG_PERFCNT6,
237 MISCREG_PERFCNT7,
238
239 MISCREG_ERRCTL = 208, //Bank 26: 208-215
240
241 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
242 MISCREG_CACHEERR1,
243 MISCREG_CACHEERR2,
244 MISCREG_CACHEERR3,
245
246 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
247 MISCREG_DATALO1,
248 MISCREG_TAGLO2,
249 MISCREG_DATALO3,
250 MISCREG_TAGLO4,
251 MISCREG_DATALO5,
252 MISCREG_TAGLO6,
253 MISCREG_DATALO7,
254
255 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
256 MISCREG_DATAHI1,
257 MISCREG_TAGHI2,
258 MISCREG_DATAHI3,
259 MISCREG_TAGHI4,
260 MISCREG_DATAHI5,
261 MISCREG_TAGHI6,
262 MISCREG_DATAHI7,
263
264
265 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
266
267 MISCREG_DESAVE = 248, //Bank 31: 248-256
268
269 MISCREG_LLFLAG = 257,
270 MISCREG_TP_VALUE,
271
272 MISCREG_NUMREGS
273};
274
275const int NumMiscRegs = MISCREG_NUMREGS;
276
277// These help enumerate all the registers for dependence tracking.
278const int FP_Reg_Base = NumIntRegs;
58
59const uint32_t MIPS32_QNAN = 0x7fbfffff;
60const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
61
62enum FPControlRegNums {
63 FLOATREG_FIR = NumFloatArchRegs,
64 FLOATREG_FCCR,
65 FLOATREG_FEXR,
66 FLOATREG_FENR,
67 FLOATREG_FCSR
68};
69
70enum FCSRBits {
71 Inexact = 1,
72 Underflow,
73 Overflow,
74 DivideByZero,
75 Invalid,
76 Unimplemented
77};
78
79enum FCSRFields {
80 Flag_Field = 1,
81 Enable_Field = 6,
82 Cause_Field = 11
83};
84
85enum MiscIntRegNums {
86 INTREG_LO = NumIntArchRegs,
87 INTREG_DSP_LO0 = INTREG_LO,
88 INTREG_HI,
89 INTREG_DSP_HI0 = INTREG_HI,
90 INTREG_DSP_ACX0,
91 INTREG_DSP_LO1,
92 INTREG_DSP_HI1,
93 INTREG_DSP_ACX1,
94 INTREG_DSP_LO2,
95 INTREG_DSP_HI2,
96 INTREG_DSP_ACX2,
97 INTREG_DSP_LO3,
98 INTREG_DSP_HI3,
99 INTREG_DSP_ACX3,
100 INTREG_DSP_CONTROL
101};
102
103// semantically meaningful register indices
104const int ZeroReg = 0;
105const int AssemblerReg = 1;
106const int SyscallSuccessReg = 7;
107const int FirstArgumentReg = 4;
108const int ReturnValueReg = 2;
109
110const int KernelReg0 = 26;
111const int KernelReg1 = 27;
112const int GlobalPointerReg = 28;
113const int StackPointerReg = 29;
114const int FramePointerReg = 30;
115const int ReturnAddressReg = 31;
116
117const int SyscallPseudoReturnReg = 3;
118
119// Enumerate names for 'Control' Registers in the CPU
120// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
121// (Register Number-Register Select) Summary of Register
122//------------------------------------------------------
123// The first set of names classify the CP0 names as Register Banks
124// for easy indexing when using the 'RD + SEL' index combination
125// in CP0 instructions.
126enum MiscRegIndex{
127 MISCREG_INDEX = 0, //Bank 0: 0 - 3
128 MISCREG_MVP_CONTROL,
129 MISCREG_MVP_CONF0,
130 MISCREG_MVP_CONF1,
131
132 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
133 MISCREG_VPE_CONTROL,
134 MISCREG_VPE_CONF0,
135 MISCREG_VPE_CONF1,
136 MISCREG_YQMASK,
137 MISCREG_VPE_SCHEDULE,
138 MISCREG_VPE_SCHEFBACK,
139 MISCREG_VPE_OPT,
140
141 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
142 MISCREG_TC_STATUS,
143 MISCREG_TC_BIND,
144 MISCREG_TC_RESTART,
145 MISCREG_TC_HALT,
146 MISCREG_TC_CONTEXT,
147 MISCREG_TC_SCHEDULE,
148 MISCREG_TC_SCHEFBACK,
149
150 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
151
152 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
153 MISCREG_CONTEXT_CONFIG,
154
155 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
156 MISCREG_PAGEGRAIN = 41,
157
158 MISCREG_WIRED = 48, //Bank 6:48-55
159 MISCREG_SRS_CONF0,
160 MISCREG_SRS_CONF1,
161 MISCREG_SRS_CONF2,
162 MISCREG_SRS_CONF3,
163 MISCREG_SRS_CONF4,
164
165 MISCREG_HWRENA = 56, //Bank 7: 56-63
166
167 MISCREG_BADVADDR = 64, //Bank 8: 64-71
168
169 MISCREG_COUNT = 72, //Bank 9: 72-79
170
171 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
172
173 MISCREG_COMPARE = 88, //Bank 11: 88-95
174
175 MISCREG_STATUS = 96, //Bank 12: 96-103
176 MISCREG_INTCTL,
177 MISCREG_SRSCTL,
178 MISCREG_SRSMAP,
179
180 MISCREG_CAUSE = 104, //Bank 13: 104-111
181
182 MISCREG_EPC = 112, //Bank 14: 112-119
183
184 MISCREG_PRID = 120, //Bank 15: 120-127,
185 MISCREG_EBASE,
186
187 MISCREG_CONFIG = 128, //Bank 16: 128-135
188 MISCREG_CONFIG1,
189 MISCREG_CONFIG2,
190 MISCREG_CONFIG3,
191 MISCREG_CONFIG4,
192 MISCREG_CONFIG5,
193 MISCREG_CONFIG6,
194 MISCREG_CONFIG7,
195
196
197 MISCREG_LLADDR = 136, //Bank 17: 136-143
198
199 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
200 MISCREG_WATCHLO1,
201 MISCREG_WATCHLO2,
202 MISCREG_WATCHLO3,
203 MISCREG_WATCHLO4,
204 MISCREG_WATCHLO5,
205 MISCREG_WATCHLO6,
206 MISCREG_WATCHLO7,
207
208 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
209 MISCREG_WATCHHI1,
210 MISCREG_WATCHHI2,
211 MISCREG_WATCHHI3,
212 MISCREG_WATCHHI4,
213 MISCREG_WATCHHI5,
214 MISCREG_WATCHHI6,
215 MISCREG_WATCHHI7,
216
217 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
218
219 //Bank 21: 168-175
220
221 //Bank 22: 176-183
222
223 MISCREG_DEBUG = 184, //Bank 23: 184-191
224 MISCREG_TRACE_CONTROL1,
225 MISCREG_TRACE_CONTROL2,
226 MISCREG_USER_TRACE_DATA,
227 MISCREG_TRACE_BPC,
228
229 MISCREG_DEPC = 192, //Bank 24: 192-199
230
231 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
232 MISCREG_PERFCNT1,
233 MISCREG_PERFCNT2,
234 MISCREG_PERFCNT3,
235 MISCREG_PERFCNT4,
236 MISCREG_PERFCNT5,
237 MISCREG_PERFCNT6,
238 MISCREG_PERFCNT7,
239
240 MISCREG_ERRCTL = 208, //Bank 26: 208-215
241
242 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
243 MISCREG_CACHEERR1,
244 MISCREG_CACHEERR2,
245 MISCREG_CACHEERR3,
246
247 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
248 MISCREG_DATALO1,
249 MISCREG_TAGLO2,
250 MISCREG_DATALO3,
251 MISCREG_TAGLO4,
252 MISCREG_DATALO5,
253 MISCREG_TAGLO6,
254 MISCREG_DATALO7,
255
256 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
257 MISCREG_DATAHI1,
258 MISCREG_TAGHI2,
259 MISCREG_DATAHI3,
260 MISCREG_TAGHI4,
261 MISCREG_DATAHI5,
262 MISCREG_TAGHI6,
263 MISCREG_DATAHI7,
264
265
266 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
267
268 MISCREG_DESAVE = 248, //Bank 31: 248-256
269
270 MISCREG_LLFLAG = 257,
271 MISCREG_TP_VALUE,
272
273 MISCREG_NUMREGS
274};
275
276const int NumMiscRegs = MISCREG_NUMREGS;
277
278// These help enumerate all the registers for dependence tracking.
279const int FP_Reg_Base = NumIntRegs;
279const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
280const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
281const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
280const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
281
282const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
283
284typedef uint16_t RegIndex;
285
286typedef uint32_t IntReg;
287
288// floating point register file entry type
289typedef uint32_t FloatRegBits;
290typedef float FloatReg;
291
292// cop-0/cop-1 system control register
293typedef uint64_t MiscReg;
294
282const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
283
284const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
285
286typedef uint16_t RegIndex;
287
288typedef uint32_t IntReg;
289
290// floating point register file entry type
291typedef uint32_t FloatRegBits;
292typedef float FloatReg;
293
294// cop-0/cop-1 system control register
295typedef uint64_t MiscReg;
296
297// dummy typedef since we don't have CC regs
298typedef uint8_t CCReg;
299
295typedef union {
296 IntReg intreg;
297 FloatReg fpreg;
298 MiscReg ctrlreg;
299} AnyReg;
300
301} // namespace MipsISA
302
303#endif
300typedef union {
301 IntReg intreg;
302 FloatReg fpreg;
303 MiscReg ctrlreg;
304} AnyReg;
305
306} // namespace MipsISA
307
308#endif