1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/generated/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46using MipsISAInst::MaxMiscDestRegs;
47
48// Constants Related to the number of registers
49const int NumIntArchRegs = 32;
50const int NumIntSpecialRegs = 9;
51const int NumFloatArchRegs = 32;
52const int NumFloatSpecialRegs = 5;
53
54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
57
58const uint32_t MIPS32_QNAN = 0x7fbfffff;
59const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
60
61enum FPControlRegNums {
62 FLOATREG_FIR = NumFloatArchRegs,
63 FLOATREG_FCCR,
64 FLOATREG_FEXR,
65 FLOATREG_FENR,
66 FLOATREG_FCSR
67};
68
69enum FCSRBits {
70 Inexact = 1,
71 Underflow,
72 Overflow,
73 DivideByZero,
74 Invalid,
75 Unimplemented
76};
77
78enum FCSRFields {
79 Flag_Field = 1,
80 Enable_Field = 6,
81 Cause_Field = 11
82};
83
84enum MiscIntRegNums {
85 INTREG_LO = NumIntArchRegs,
86 INTREG_DSP_LO0 = INTREG_LO,
87 INTREG_HI,
88 INTREG_DSP_HI0 = INTREG_HI,
89 INTREG_DSP_ACX0,
90 INTREG_DSP_LO1,
91 INTREG_DSP_HI1,
92 INTREG_DSP_ACX1,
93 INTREG_DSP_LO2,
94 INTREG_DSP_HI2,
95 INTREG_DSP_ACX2,
96 INTREG_DSP_LO3,
97 INTREG_DSP_HI3,
98 INTREG_DSP_ACX3,
99 INTREG_DSP_CONTROL
100};
101
102// semantically meaningful register indices
103const int ZeroReg = 0;
104const int AssemblerReg = 1;
105const int SyscallSuccessReg = 7;
106const int FirstArgumentReg = 4;
107const int ReturnValueReg = 2;
108
109const int KernelReg0 = 26;
110const int KernelReg1 = 27;
111const int GlobalPointerReg = 28;
112const int StackPointerReg = 29;
113const int FramePointerReg = 30;
114const int ReturnAddressReg = 31;
115
116const int SyscallPseudoReturnReg = 3;
117
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/generated/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46using MipsISAInst::MaxMiscDestRegs;
47
48// Constants Related to the number of registers
49const int NumIntArchRegs = 32;
50const int NumIntSpecialRegs = 9;
51const int NumFloatArchRegs = 32;
52const int NumFloatSpecialRegs = 5;
53
54const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
55const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
56const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
57
58const uint32_t MIPS32_QNAN = 0x7fbfffff;
59const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
60
61enum FPControlRegNums {
62 FLOATREG_FIR = NumFloatArchRegs,
63 FLOATREG_FCCR,
64 FLOATREG_FEXR,
65 FLOATREG_FENR,
66 FLOATREG_FCSR
67};
68
69enum FCSRBits {
70 Inexact = 1,
71 Underflow,
72 Overflow,
73 DivideByZero,
74 Invalid,
75 Unimplemented
76};
77
78enum FCSRFields {
79 Flag_Field = 1,
80 Enable_Field = 6,
81 Cause_Field = 11
82};
83
84enum MiscIntRegNums {
85 INTREG_LO = NumIntArchRegs,
86 INTREG_DSP_LO0 = INTREG_LO,
87 INTREG_HI,
88 INTREG_DSP_HI0 = INTREG_HI,
89 INTREG_DSP_ACX0,
90 INTREG_DSP_LO1,
91 INTREG_DSP_HI1,
92 INTREG_DSP_ACX1,
93 INTREG_DSP_LO2,
94 INTREG_DSP_HI2,
95 INTREG_DSP_ACX2,
96 INTREG_DSP_LO3,
97 INTREG_DSP_HI3,
98 INTREG_DSP_ACX3,
99 INTREG_DSP_CONTROL
100};
101
102// semantically meaningful register indices
103const int ZeroReg = 0;
104const int AssemblerReg = 1;
105const int SyscallSuccessReg = 7;
106const int FirstArgumentReg = 4;
107const int ReturnValueReg = 2;
108
109const int KernelReg0 = 26;
110const int KernelReg1 = 27;
111const int GlobalPointerReg = 28;
112const int StackPointerReg = 29;
113const int FramePointerReg = 30;
114const int ReturnAddressReg = 31;
115
116const int SyscallPseudoReturnReg = 3;
117
|
127// Enumerate names for 'Control' Registers in the CPU
128// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
129// (Register Number-Register Select) Summary of Register
130//------------------------------------------------------
131// The first set of names classify the CP0 names as Register Banks
132// for easy indexing when using the 'RD + SEL' index combination
133// in CP0 instructions.
134enum MiscRegIndex{
135 MISCREG_INDEX = 0, //Bank 0: 0 - 3
136 MISCREG_MVP_CONTROL,
137 MISCREG_MVP_CONF0,
138 MISCREG_MVP_CONF1,
139
140 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
141 MISCREG_VPE_CONTROL,
142 MISCREG_VPE_CONF0,
143 MISCREG_VPE_CONF1,
144 MISCREG_YQMASK,
145 MISCREG_VPE_SCHEDULE,
146 MISCREG_VPE_SCHEFBACK,
147 MISCREG_VPE_OPT,
148
149 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
150 MISCREG_TC_STATUS,
151 MISCREG_TC_BIND,
152 MISCREG_TC_RESTART,
153 MISCREG_TC_HALT,
154 MISCREG_TC_CONTEXT,
155 MISCREG_TC_SCHEDULE,
156 MISCREG_TC_SCHEFBACK,
157
158 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
159
160 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
161 MISCREG_CONTEXT_CONFIG,
162
163 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
164 MISCREG_PAGEGRAIN = 41,
165
166 MISCREG_WIRED = 48, //Bank 6:48-55
167 MISCREG_SRS_CONF0,
168 MISCREG_SRS_CONF1,
169 MISCREG_SRS_CONF2,
170 MISCREG_SRS_CONF3,
171 MISCREG_SRS_CONF4,
172
173 MISCREG_HWRENA = 56, //Bank 7: 56-63
174
175 MISCREG_BADVADDR = 64, //Bank 8: 64-71
176
177 MISCREG_COUNT = 72, //Bank 9: 72-79
178
179 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
180
181 MISCREG_COMPARE = 88, //Bank 11: 88-95
182
183 MISCREG_STATUS = 96, //Bank 12: 96-103
184 MISCREG_INTCTL,
185 MISCREG_SRSCTL,
186 MISCREG_SRSMAP,
187
188 MISCREG_CAUSE = 104, //Bank 13: 104-111
189
190 MISCREG_EPC = 112, //Bank 14: 112-119
191
192 MISCREG_PRID = 120, //Bank 15: 120-127,
193 MISCREG_EBASE,
194
195 MISCREG_CONFIG = 128, //Bank 16: 128-135
196 MISCREG_CONFIG1,
197 MISCREG_CONFIG2,
198 MISCREG_CONFIG3,
199 MISCREG_CONFIG4,
200 MISCREG_CONFIG5,
201 MISCREG_CONFIG6,
202 MISCREG_CONFIG7,
203
204
205 MISCREG_LLADDR = 136, //Bank 17: 136-143
206
207 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
208 MISCREG_WATCHLO1,
209 MISCREG_WATCHLO2,
210 MISCREG_WATCHLO3,
211 MISCREG_WATCHLO4,
212 MISCREG_WATCHLO5,
213 MISCREG_WATCHLO6,
214 MISCREG_WATCHLO7,
215
216 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
217 MISCREG_WATCHHI1,
218 MISCREG_WATCHHI2,
219 MISCREG_WATCHHI3,
220 MISCREG_WATCHHI4,
221 MISCREG_WATCHHI5,
222 MISCREG_WATCHHI6,
223 MISCREG_WATCHHI7,
224
225 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
226
227 //Bank 21: 168-175
228
229 //Bank 22: 176-183
230
231 MISCREG_DEBUG = 184, //Bank 23: 184-191
232 MISCREG_TRACE_CONTROL1,
233 MISCREG_TRACE_CONTROL2,
234 MISCREG_USER_TRACE_DATA,
235 MISCREG_TRACE_BPC,
236
237 MISCREG_DEPC = 192, //Bank 24: 192-199
238
239 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
240 MISCREG_PERFCNT1,
241 MISCREG_PERFCNT2,
242 MISCREG_PERFCNT3,
243 MISCREG_PERFCNT4,
244 MISCREG_PERFCNT5,
245 MISCREG_PERFCNT6,
246 MISCREG_PERFCNT7,
247
248 MISCREG_ERRCTL = 208, //Bank 26: 208-215
249
250 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
251 MISCREG_CACHEERR1,
252 MISCREG_CACHEERR2,
253 MISCREG_CACHEERR3,
254
255 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
256 MISCREG_DATALO1,
257 MISCREG_TAGLO2,
258 MISCREG_DATALO3,
259 MISCREG_TAGLO4,
260 MISCREG_DATALO5,
261 MISCREG_TAGLO6,
262 MISCREG_DATALO7,
263
264 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
265 MISCREG_DATAHI1,
266 MISCREG_TAGHI2,
267 MISCREG_DATAHI3,
268 MISCREG_TAGHI4,
269 MISCREG_DATAHI5,
270 MISCREG_TAGHI6,
271 MISCREG_DATAHI7,
272
273
274 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
275
276 MISCREG_DESAVE = 248, //Bank 31: 248-256
277
278 MISCREG_LLFLAG = 257,
279 MISCREG_TP_VALUE,
280
281 MISCREG_NUMREGS
282};
283
| 118// Enumerate names for 'Control' Registers in the CPU
119// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
120// (Register Number-Register Select) Summary of Register
121//------------------------------------------------------
122// The first set of names classify the CP0 names as Register Banks
123// for easy indexing when using the 'RD + SEL' index combination
124// in CP0 instructions.
125enum MiscRegIndex{
126 MISCREG_INDEX = 0, //Bank 0: 0 - 3
127 MISCREG_MVP_CONTROL,
128 MISCREG_MVP_CONF0,
129 MISCREG_MVP_CONF1,
130
131 MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15
132 MISCREG_VPE_CONTROL,
133 MISCREG_VPE_CONF0,
134 MISCREG_VPE_CONF1,
135 MISCREG_YQMASK,
136 MISCREG_VPE_SCHEDULE,
137 MISCREG_VPE_SCHEFBACK,
138 MISCREG_VPE_OPT,
139
140 MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23
141 MISCREG_TC_STATUS,
142 MISCREG_TC_BIND,
143 MISCREG_TC_RESTART,
144 MISCREG_TC_HALT,
145 MISCREG_TC_CONTEXT,
146 MISCREG_TC_SCHEDULE,
147 MISCREG_TC_SCHEFBACK,
148
149 MISCREG_ENTRYLO1 = 24, // Bank 3: 24
150
151 MISCREG_CONTEXT = 32, // Bank 4: 32 - 33
152 MISCREG_CONTEXT_CONFIG,
153
154 MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
155 MISCREG_PAGEGRAIN = 41,
156
157 MISCREG_WIRED = 48, //Bank 6:48-55
158 MISCREG_SRS_CONF0,
159 MISCREG_SRS_CONF1,
160 MISCREG_SRS_CONF2,
161 MISCREG_SRS_CONF3,
162 MISCREG_SRS_CONF4,
163
164 MISCREG_HWRENA = 56, //Bank 7: 56-63
165
166 MISCREG_BADVADDR = 64, //Bank 8: 64-71
167
168 MISCREG_COUNT = 72, //Bank 9: 72-79
169
170 MISCREG_ENTRYHI = 80, //Bank 10: 80-87
171
172 MISCREG_COMPARE = 88, //Bank 11: 88-95
173
174 MISCREG_STATUS = 96, //Bank 12: 96-103
175 MISCREG_INTCTL,
176 MISCREG_SRSCTL,
177 MISCREG_SRSMAP,
178
179 MISCREG_CAUSE = 104, //Bank 13: 104-111
180
181 MISCREG_EPC = 112, //Bank 14: 112-119
182
183 MISCREG_PRID = 120, //Bank 15: 120-127,
184 MISCREG_EBASE,
185
186 MISCREG_CONFIG = 128, //Bank 16: 128-135
187 MISCREG_CONFIG1,
188 MISCREG_CONFIG2,
189 MISCREG_CONFIG3,
190 MISCREG_CONFIG4,
191 MISCREG_CONFIG5,
192 MISCREG_CONFIG6,
193 MISCREG_CONFIG7,
194
195
196 MISCREG_LLADDR = 136, //Bank 17: 136-143
197
198 MISCREG_WATCHLO0 = 144, //Bank 18: 144-151
199 MISCREG_WATCHLO1,
200 MISCREG_WATCHLO2,
201 MISCREG_WATCHLO3,
202 MISCREG_WATCHLO4,
203 MISCREG_WATCHLO5,
204 MISCREG_WATCHLO6,
205 MISCREG_WATCHLO7,
206
207 MISCREG_WATCHHI0 = 152, //Bank 19: 152-159
208 MISCREG_WATCHHI1,
209 MISCREG_WATCHHI2,
210 MISCREG_WATCHHI3,
211 MISCREG_WATCHHI4,
212 MISCREG_WATCHHI5,
213 MISCREG_WATCHHI6,
214 MISCREG_WATCHHI7,
215
216 MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
217
218 //Bank 21: 168-175
219
220 //Bank 22: 176-183
221
222 MISCREG_DEBUG = 184, //Bank 23: 184-191
223 MISCREG_TRACE_CONTROL1,
224 MISCREG_TRACE_CONTROL2,
225 MISCREG_USER_TRACE_DATA,
226 MISCREG_TRACE_BPC,
227
228 MISCREG_DEPC = 192, //Bank 24: 192-199
229
230 MISCREG_PERFCNT0 = 200, //Bank 25: 200-207
231 MISCREG_PERFCNT1,
232 MISCREG_PERFCNT2,
233 MISCREG_PERFCNT3,
234 MISCREG_PERFCNT4,
235 MISCREG_PERFCNT5,
236 MISCREG_PERFCNT6,
237 MISCREG_PERFCNT7,
238
239 MISCREG_ERRCTL = 208, //Bank 26: 208-215
240
241 MISCREG_CACHEERR0 = 216, //Bank 27: 216-223
242 MISCREG_CACHEERR1,
243 MISCREG_CACHEERR2,
244 MISCREG_CACHEERR3,
245
246 MISCREG_TAGLO0 = 224, //Bank 28: 224-231
247 MISCREG_DATALO1,
248 MISCREG_TAGLO2,
249 MISCREG_DATALO3,
250 MISCREG_TAGLO4,
251 MISCREG_DATALO5,
252 MISCREG_TAGLO6,
253 MISCREG_DATALO7,
254
255 MISCREG_TAGHI0 = 232, //Bank 29: 232-239
256 MISCREG_DATAHI1,
257 MISCREG_TAGHI2,
258 MISCREG_DATAHI3,
259 MISCREG_TAGHI4,
260 MISCREG_DATAHI5,
261 MISCREG_TAGHI6,
262 MISCREG_DATAHI7,
263
264
265 MISCREG_ERROR_EPC = 240, //Bank 30: 240-247
266
267 MISCREG_DESAVE = 248, //Bank 31: 248-256
268
269 MISCREG_LLFLAG = 257,
270 MISCREG_TP_VALUE,
271
272 MISCREG_NUMREGS
273};
274
|