1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
--- 29 unchanged lines hidden (view full) ---
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46
47// Constants Related to the number of registers
48const int NumIntArchRegs = 32;
49const int NumIntSpecialRegs = 9;
50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
--- 256 unchanged lines hidden ---
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
--- 29 unchanged lines hidden (view full) ---
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46
47// Constants Related to the number of registers
48const int NumIntArchRegs = 32;
49const int NumIntSpecialRegs = 9;
50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
--- 256 unchanged lines hidden ---