1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/generic/vec_reg.hh"
36#include "arch/mips/generated/max_inst_regs.hh"
37#include "base/logging.hh"
38#include "base/types.hh"
39
40class ThreadContext;
41
42namespace MipsISA

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50const int NumIntArchRegs = 32;
51const int NumIntSpecialRegs = 9;
52const int NumFloatArchRegs = 32;
53const int NumFloatSpecialRegs = 5;
54
55const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
56const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
57const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
58const int NumCCRegs = 0;
59
60const uint32_t MIPS32_QNAN = 0x7fbfffff;
61const uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff);
62
63enum FPControlRegNums {
64 FLOATREG_FIR = NumFloatArchRegs,
65 FLOATREG_FCCR,

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284typedef RegVal FloatRegBits;
285
286// cop-0/cop-1 system control register
287typedef RegVal MiscReg;
288
289// dummy typedef since we don't have CC regs
290typedef uint8_t CCReg;
291
292// dummy typedefs since we don't have vector regs
293constexpr unsigned NumVecElemPerVecReg = 2;
294using VecElem = uint32_t;
295using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
296using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
297using VecRegContainer = VecReg::Container;
298// This has to be one to prevent warnings that are treated as errors
299constexpr unsigned NumVecRegs = 1;
300
301} // namespace MipsISA
302
303#endif