pra_constants.hh (5222:bb733a878f85) | pra_constants.hh (6376:eaf61ef6a8f2) |
---|---|
1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Jaidev Patwardhan 29 */ 30 31#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__ 32#define __ARCH_MIPS_PRA_CONSTANTS_HH__ 33 34#include "arch/mips/types.hh" | 1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Jaidev Patwardhan 29 */ 30 31#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__ 32#define __ARCH_MIPS_PRA_CONSTANTS_HH__ 33 34#include "arch/mips/types.hh" |
35//#include "config/full_system.hh" | 35#include "base/bitunion.hh" |
36 37namespace MipsISA 38{ | 36 37namespace MipsISA 38{ |
39 // See MIPS32(R) Architecture Reference Manual Volume - III 40 // This header file uses definitions from Revision 2.50 | |
41 | 39 |
42 // Index Status Register - CP0 Reg 0, Sel 0 | 40BitUnion32(IndexReg) 41 Bitfield<31> p; 42 // Need to figure out how to put in the TLB specific bits here 43 // For now, we assume that the entire length is used by the index 44 // field In reality, Index_HI = N-1, where 45 // N = Ceiling(log2(TLB Entries)) 46 Bitfield<30, 0> index; 47EndBitUnion(IndexReg) |
43 | 48 |
44 const unsigned Index_P_HI = 31; 45 const unsigned Index_P_LO = 31; 46 // Need to figure out how to put in the TLB specific bits here 47 // For now, we assume that the entire length is used by the index field 48 // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N 49 const unsigned Index_HI = 30; 50 const unsigned Index_LO = 0; | 49BitUnion32(RandomReg) 50 // This has a problem similar to the IndexReg index field. We'll keep 51 // both consistent at 30 for now 52 Bitfield<30, 0> random; 53EndBitUnion(RandomReg) |
51 | 54 |
52 // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh | 55BitUnion64(EntryLoReg) 56 Bitfield<63, 30> fill; 57 Bitfield<29, 6> pfn; // Page frame number 58 Bitfield<5, 3> c; // Coherency attribute 59 Bitfield<2> d; // Dirty Bit 60 Bitfield<1> v; // Valid Bit 61 Bitfield<0> g; // Global Bit 62EndBitUnion(EntryLoReg) |
53 | 63 |
54 // Random Register - CP0 Reg 1, Sel 0 55 // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now 56 const unsigned Random_HI = 30; 57 const unsigned Random_LO = 0; | 64BitUnion64(ContextReg) 65 Bitfield<63, 23> pteBase; 66 Bitfield<22, 4> badVPN2; 67 // Bits 3-0 are 0 68EndBitUnion(ContextReg) |
58 | 69 |
59 // EntryLo0 - CP0 Reg2, Sel 0 - Table 8-6, ARM Vol-3 60 const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III 61 const unsigned EntryLo0_Fill_LO = 30; 62 const unsigned EntryLo0_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 63 const unsigned EntryLo0_PFN_LO = 6; 64 const unsigned EntryLo0_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 65 const unsigned EntryLo0_C_LO = 3; 66 const unsigned EntryLo0_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 67 const unsigned EntryLo0_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 68 const unsigned EntryLo0_V_HI = 1; // Valid Bit 69 const unsigned EntryLo0_V_LO = 1; // Valid Bit 70 const unsigned EntryLo0_G_HI = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 71 const unsigned EntryLo0_G_LO = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 72 // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1 73 // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are 74 // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1 75 // reflect the state of the TLB G bit. | 70BitUnion32(PageMaskReg) 71 // Bits 31-29 are 0 72 Bitfield<28, 13> mask; 73 Bitfield<12, 11> maskx; 74 // Bits 10-0 are zero 75EndBitUnion(PageMaskReg) |
76 | 76 |
77 // EntryLo1 - CP0 Reg3, Sel 0 78 const unsigned EntryLo1_G_HI = 0; 79 const unsigned EntryLo1_G_LO = 0; 80 const unsigned EntryLo1_V_HI = 1; // Valid Bit 81 const unsigned EntryLo1_V_LO = 1; // Valid Bit 82 const unsigned EntryLo1_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 83 const unsigned EntryLo1_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 84 const unsigned EntryLo1_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 85 const unsigned EntryLo1_C_LO = 3; 86 const unsigned EntryLo1_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 87 const unsigned EntryLo1_PFN_LO = 6; 88 const unsigned EntryLo1_Fill_LO = 30; 89 const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III | 77BitUnion32(PageGrainReg) 78 Bitfield<31, 30> aseUp; 79 Bitfield<29> elpa; 80 Bitfield<28> esp; 81 // Bits 27-13 are zeros 82 Bitfield<12, 8> aseDn; 83 // Bits 7-0 are zeros 84EndBitUnion(PageGrainReg) |
90 | 85 |
86BitUnion32(WiredReg) 87 // See note on Index register above 88 Bitfield<30, 0> wired; 89EndBitUnion(WiredReg) |
|
91 | 90 |
92 // Context Register - CP0 Reg 4, Sel 0 93 const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array 94 const unsigned Context_PTEBase_LO = 23; 95 const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the 96 const unsigned Context_BadVPN2_LO = 4; // virtual address 97 // Bits 3-0 are zeros | 91BitUnion32(HWREnaReg) 92 Bitfield<31, 30> impl; 93 Bitfield<3, 0> mask; 94EndBitUnion(HWREnaReg) |
98 | 95 |
99 // PageMask Register - CP0 Reg 5, Sel 0 100 // Bits 31-29 are 0 101 const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that 102 const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match 103 const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III 104 const unsigned PageMask_MaskX_LO = 11; 105 // Bits 10-0 are zero | 96BitUnion64(EntryHiReg) 97 Bitfield<63, 62> r; 98 Bitfield<61, 40> fill; 99 Bitfield<39, 13> vpn2; 100 Bitfield<12, 11> vpn2x; 101 Bitfield<7, 0> asid; 102EndBitUnion(EntryHiReg) |
106 | 103 |
104BitUnion32(StatusReg) 105 SubBitUnion(cu, 31, 28) 106 Bitfield<31> cu3; 107 Bitfield<30> cu2; 108 Bitfield<29> cu1; 109 Bitfield<28> cu0; 110 EndSubBitUnion(cu) 111 Bitfield<27> rp; 112 Bitfield<26> fr; 113 Bitfield<25> re; 114 Bitfield<24> mx; 115 Bitfield<23> px; 116 Bitfield<22> bev; 117 Bitfield<21> ts; 118 Bitfield<20> sr; 119 Bitfield<19> nmi; 120 // Bit 18 is zero 121 Bitfield<17, 16> impl; 122 Bitfield<15, 10> ipl; 123 Bitfield<15> im7; 124 Bitfield<14> im6; 125 Bitfield<13> im5; 126 Bitfield<12> im4; 127 Bitfield<11> im3; 128 Bitfield<10> im2; 129 Bitfield<9> im1; 130 Bitfield<8> im0; 131 Bitfield<7> kx; 132 Bitfield<6> sx; 133 Bitfield<5> ux; 134 Bitfield<4, 3> ksu; 135 Bitfield<4> um; 136 Bitfield<3> r0; 137 Bitfield<2> erl; 138 Bitfield<1> exl; 139 Bitfield<0> ie; 140EndBitUnion(StatusReg) |
|
107 | 141 |
108 // PageGrain Register - CP0 Reg 5, Sel 1 109 const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS) 110 const unsigned PageGrain_ASE_UP_LO = 30; // 111 const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32 112 const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 113 const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 114 const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 115 const unsigned PageGrain_ASE_DN_HI = 12; 116 const unsigned PageGrain_ASE_DN_LO = 8; 117 // Bits 27-13, 7-0 are zeros | 142BitUnion32(IntCtlReg) 143 Bitfield<31, 29> ipti; 144 Bitfield<28, 26> ippci; 145 // Bits 26-10 are zeros 146 Bitfield<9, 5> vs; 147 // Bits 4-0 are zeros 148EndBitUnion(IntCtlReg) |
118 | 149 |
119 // Wired Register - CPO Reg 6, Sel 0 120 // See note on Index register (CP0, Sel0) above 121 const unsigned Wired_HI = 30; 122 const unsigned Wired_LO = 0; | 150BitUnion32(SRSCtlReg) 151 // Bits 31-30 are zeros 152 Bitfield<29, 26> hss; 153 // Bits 25-22 are zeros 154 Bitfield<21, 18> eicss; 155 // Bits 17-16 are zeros 156 Bitfield<15, 12> ess; 157 // Bits 11-10 are zeros 158 Bitfield<9, 6> pss; 159 // Bits 5-4 are zeros 160 Bitfield<3, 0> css; 161EndBitUnion(SRSCtlReg) |
123 | 162 |
163BitUnion32(SRSMapReg) 164 Bitfield<31, 28> ssv7; 165 Bitfield<27, 24> ssv6; 166 Bitfield<23, 20> ssv5; 167 Bitfield<19, 16> ssv4; 168 Bitfield<15, 12> ssv3; 169 Bitfield<11, 8> ssv2; 170 Bitfield<7, 4> ssv1; 171 Bitfield<3, 0> ssv0; 172EndBitUnion(SRSMapReg) |
|
124 | 173 |
125 // HWREna Register - CP0 Reg 7, Sel 0 126 const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31 127 const unsigned HWREna_IMPL_LO = 30; // and 30 128 const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible 129 const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details | 174BitUnion32(CauseReg) 175 Bitfield<31> bd; 176 Bitfield<30> ti; 177 Bitfield<29, 28> ce; 178 Bitfield<27> dc; 179 Bitfield<26> pci; 180 // Bits 25-24 are zeros 181 Bitfield<23> iv; 182 Bitfield<22> wp; 183 // Bits 21-16 are zeros 184 Bitfield<15, 10> ripl; 185 Bitfield<15> ip7; 186 Bitfield<14> ip6; 187 Bitfield<13> ip5; 188 Bitfield<12> ip4; 189 Bitfield<11> ip3; 190 Bitfield<10> ip2; 191 Bitfield<9> ip1; 192 Bitfield<8> ip0; 193 // Bit 7 is zero 194 Bitfield<6, 2> excCode; 195 // Bits 1-0 are zeros 196EndBitUnion(CauseReg) |
130 | 197 |
198BitUnion32(PRIdReg) 199 Bitfield<31, 24> coOp; 200 Bitfield<23, 16> coId; 201 Bitfield<15, 8> procId; 202 Bitfield<7, 0> rev; 203EndBitUnion(PRIdReg) |
|
131 | 204 |
132 // BadVAddr Register - CP0 Reg 8, Sel 0 133 const unsigned BadVAddr_HI = 31; 134 const unsigned BadVAddr_LO = 0; | 205BitUnion32(EBaseReg) 206 // Bit 31 is one 207 // Bit 30 is zero 208 Bitfield<29, 12> exceptionBase; 209 // Bits 11-10 are zeros 210 Bitfield<9, 9> cpuNum; 211EndBitUnion(EBaseReg) |
135 | 212 |
136 // Count Register - CP0 Reg 9, Sel 0 137 const unsigned Count_HI = 31; 138 const unsigned Count_LO = 0; | 213BitUnion32(ConfigReg) 214 Bitfield<31> m; 215 Bitfield<30, 28> k23; 216 Bitfield<27, 25> ku; 217 Bitfield<24, 16> impl; 218 Bitfield<15> be; 219 Bitfield<14, 13> at; 220 Bitfield<12, 10> ar; 221 Bitfield<9, 7> mt; 222 // Bits 6-4 are zeros 223 Bitfield<3> vi; 224 Bitfield<2, 0> k0; 225EndBitUnion(ConfigReg) |
139 | 226 |
140 // EntryHI Register - CP0 Reg 10, Sel 0 141 const unsigned EntryHi_VPN2_HI = 31; // This field is written by hardware on a TLB exception or on a TLB read 142 const unsigned EntryHi_VPN2_LO = 13; // and is written by software before a TLB write 143 const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages 144 const unsigned EntryHi_VPN2X_LO = 11; 145 const unsigned EntryHi_ASID_HI = 7; // Address space identifier 146 const unsigned EntryHi_ASID_LO = 0; | 227BitUnion32(Config1Reg) 228 Bitfield<31> m; 229 Bitfield<30, 25> mmuSize; 230 Bitfield<24, 22> is; 231 Bitfield<21, 19> il; 232 Bitfield<18, 16> ia; 233 Bitfield<15, 13> ds; 234 Bitfield<12, 10> dl; 235 Bitfield<9, 7> da; 236 Bitfield<6> c2; 237 Bitfield<5> md; 238 Bitfield<4> pc; 239 Bitfield<3> wr; 240 Bitfield<2> ca; 241 Bitfield<1> ep; 242 Bitfield<0> fp; 243EndBitUnion(Config1Reg) |
147 | 244 |
148 // Compare Register - CP0 Reg 11, Sel 0 149 const unsigned Compare_HI = 31; // Used in conjunction with Count 150 const unsigned Compare_LO = 0; | 245BitUnion32(Config2Reg) 246 Bitfield<31> m; 247 Bitfield<30, 28> tu; 248 Bitfield<27, 24> ts; 249 Bitfield<23, 20> tl; 250 Bitfield<19, 16> ta; 251 Bitfield<15, 12> su; 252 Bitfield<11, 8> ss; 253 Bitfield<7, 4> sl; 254 Bitfield<3, 0> sa; 255EndBitUnion(Config2Reg) |
151 | 256 |
152 // Status Register - CP Reg 12, Sel 0 153 const unsigned Status_IE_HI = 0; 154 const unsigned Status_IE_LO = 0; | 257BitUnion32(Config3Reg) 258 Bitfield<31> m; 259 // Bits 30-11 are zeros 260 Bitfield<10> dspp; 261 // Bits 9-8 are zeros 262 Bitfield<7> lpa; 263 Bitfield<6> veic; 264 Bitfield<5> vint; 265 Bitfield<4> sp; 266 // Bit 3 is zero 267 Bitfield<2> mt; 268 Bitfield<1> sm; 269 Bitfield<0> tl; 270EndBitUnion(Config3Reg) |
155 | 271 |
156 const unsigned Status_EXL = 1; 157 const unsigned Status_EXL_HI = 1; 158 const unsigned Status_EXL_LO = 1; 159 const unsigned Status_ERL_HI = 2; 160 const unsigned Status_ERL_LO = 2; 161 const unsigned Status_R0 = 3; 162 const unsigned Status_UM = 4; 163 const unsigned Status_KSU_HI = 4; // R0 and UM are also aliased as KSU 164 const unsigned Status_KSU_LO = 3; 165 const unsigned Status_UX = 5; 166 const unsigned Status_SX = 6; 167 const unsigned Status_KX = 7; 168 const unsigned Status_IM0 = 8; 169 const unsigned Status_IM1 = 9; 170 const unsigned Status_IM2 = 10; 171 const unsigned Status_IM3 = 11; 172 const unsigned Status_IM4 = 12; 173 const unsigned Status_IM5 = 13; 174 const unsigned Status_IM6 = 14; 175 const unsigned Status_IM7 = 15; 176 const unsigned Status_IPL_HI = 15; // IM7..IM2 are also aliased as IPL 177 const unsigned Status_IPL_LO = 10; 178 const unsigned Status_IMPL_HI = 17; 179 const unsigned Status_IMPL_LO = 16; 180 const unsigned Status_NMI = 19; 181 const unsigned Status_SR = 20; 182 const unsigned Status_TS = 21; 183 const unsigned Status_BEV = 22; 184 const unsigned Status_BEV_HI = 22; 185 const unsigned Status_BEV_LO = 22; 186 const unsigned Status_PX = 23; 187 const unsigned Status_MX = 24; 188 const unsigned Status_RE = 25; 189 const unsigned Status_FR = 26; 190 const unsigned Status_RP = 27; 191 const unsigned Status_CU3_HI = 31; 192 const unsigned Status_CU3_LO = 31; 193 const unsigned Status_CU2_HI = 30; 194 const unsigned Status_CU2_LO = 30; 195 const unsigned Status_CU1_HI = 29; 196 const unsigned Status_CU1_LO = 29; 197 const unsigned Status_CU0_HI = 28; 198 const unsigned Status_CU0_LO = 28; | 272BitUnion64(WatchLoReg) 273 Bitfield<63, 3> vaddr; 274 Bitfield<2> i; 275 Bitfield<1> r; 276 Bitfield<0> w; 277EndBitUnion(WatchLoReg) |
199 | 278 |
200 // IntCtl Register - CP0 Reg 12, Sel 1 201 // Interrupt System status and control 202 const unsigned IntCtl_IPTI_HI = 31; 203 const unsigned IntCtl_IPTI_LO = 29; 204 const unsigned IntCtl_IPPCI_HI = 28; 205 const unsigned IntCtl_IPPCI_LO = 26; 206 const unsigned IntCtl_VS_HI = 9; 207 const unsigned IntCtl_VS_LO = 5; 208 // Bits 26-10, 4-0 are zeros | 279BitUnion32(WatchHiReg) 280 Bitfield<31> m; 281 Bitfield<30> g; 282 // Bits 29-24 are zeros 283 Bitfield<23, 16> asid; 284 // Bits 15-12 are zeros 285 Bitfield<11, 3> mask; 286 Bitfield<2> i; 287 Bitfield<1> r; 288 Bitfield<0> w; 289EndBitUnion(WatchHiReg) |
209 | 290 |
210 // SRSCtl Register - CP0 Reg 12, Sel 2 211 // Shadow Register Set Status and Control 212 const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set 213 const unsigned SRSCtl_HSS_LO=26; 214 const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set 215 const unsigned SRSCtl_EICSS_LO=18; 216 const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set 217 const unsigned SRSCtl_ESS_LO=12; 218 const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set 219 const unsigned SRSCtl_PSS_LO=6; 220 const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set 221 const unsigned SRSCtl_CSS_LO=0; | 291BitUnion32(PerfCntCtlReg) 292 Bitfield<31> m; 293 Bitfield<30> w; 294 // Bits 29-11 are zeros 295 Bitfield<10, 5> event; 296 Bitfield<4> ie; 297 Bitfield<3> u; 298 Bitfield<2> s; 299 Bitfield<1> k; 300 Bitfield<0> exl; 301EndBitUnion(PerfCntCtlReg) |
222 | 302 |
223 // SRSMap Register - CP0 Reg 12, Sel 3 224 // Shadow Set IPL mapping 225 const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0) 226 const unsigned SRSMap_SSV7_LO = 28; 227 const unsigned SRSMap_SSV6_HI = 27; 228 const unsigned SRSMap_SSV6_LO = 24; 229 const unsigned SRSMap_SSV5_HI = 23; 230 const unsigned SRSMap_SSV5_LO = 20; 231 const unsigned SRSMap_SSV4_HI = 19; 232 const unsigned SRSMap_SSV4_LO = 16; 233 const unsigned SRSMap_SSV3_HI = 15; 234 const unsigned SRSMap_SSV3_LO = 12; 235 const unsigned SRSMap_SSV2_HI = 11; 236 const unsigned SRSMap_SSV2_LO = 8; 237 const unsigned SRSMap_SSV1_HI = 7; 238 const unsigned SRSMap_SSV1_LO = 4; 239 const unsigned SRSMap_SSV0_HI = 3; 240 const unsigned SRSMap_SSV0_LO = 20; | 303BitUnion32(CacheErrReg) 304 Bitfield<31> er; 305 Bitfield<30> ec; 306 Bitfield<29> ed; 307 Bitfield<28> et; 308 Bitfield<27> es; 309 Bitfield<26> ee; 310 Bitfield<25> eb; 311 Bitfield<24, 22> impl; 312 Bitfield<22, 0> index; 313EndBitUnion(CacheErrReg) |
241 | 314 |
242 // Cause Register - CP0 Reg 13, Sel 0 243 const unsigned Cause_BD_HI = 31; 244 const unsigned Cause_BD_LO = 31; 245 const unsigned Cause_TI_HI = 30; 246 const unsigned Cause_TI_LO = 30; 247 const unsigned Cause_CE_HI = 29; 248 const unsigned Cause_CE_LO = 28; 249 const unsigned Cause_DC = 27; 250 const unsigned Cause_PCI = 26; 251 const unsigned Cause_IV = 24; 252 const unsigned Cause_WP = 23; 253 const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5 254 const unsigned Cause_RIPL_LO = 10; 255 const unsigned Cause_IP7 = 15; 256 const unsigned Cause_IP6 = 14; 257 const unsigned Cause_IP5 = 13; 258 const unsigned Cause_IP4 = 12; 259 const unsigned Cause_IP3 = 11; 260 const unsigned Cause_IP2 = 10; 261 const unsigned Cause_IP1 = 9; 262 const unsigned Cause_IP0 = 8; 263 const unsigned Cause_EXCCODE_HI = 6; 264 const unsigned Cause_EXCCODE_LO = 2; 265 // All intermediate undefined bits must be ZERO | 315BitUnion32(TagLoReg) 316 Bitfield<31, 8> pTagLo; 317 Bitfield<7, 6> pState; 318 Bitfield<5> l; 319 Bitfield<4, 3> impl; 320 // Bits 2-1 are zeros 321 Bitfield<0> p; 322EndBitUnion(TagLoReg) |
266 | 323 |
267 268 // EPC Register - CP0 Reg 14, Sel 0 269 // Exception Program Counter 270 const unsigned EPC_HI = 31; 271 const unsigned EPC_LO = 0; 272 273 // PRId Register - CP0 Reg 15, Sel 0 274 // Processor Identification register 275 const unsigned PRIdCoOp_HI = 31; 276 const unsigned PRIdCoOp_LO = 24; 277 const unsigned PRIdCoID_HI = 23; 278 const unsigned PRIdCoID_LO = 16; 279 const unsigned PRIdProc_ID_HI = 15; 280 const unsigned PRIdProc_ID_LO = 8; 281 const unsigned PRIdRev_HI = 7; 282 const unsigned PRIdRev_LO = 0; 283 284 285 // EBase Register - CP0 Reg 15, Sel 1 286 // Exception Base Register 287 const unsigned EBase_MSB = 31; // MUST BE = 1 288 const unsigned EBase_EXCEPTION_Base_HI = 29; 289 const unsigned EBase_EXCEPTION_Base_LO = 12; 290 const unsigned EBase_CPUNum_HI = 9; 291 const unsigned EBase_CPUNum_LO = 0; 292 // Undefined bits must be zero 293 294 // Config Register - CP0 Reg 16, Sel 0 295 const unsigned Config_M = 31; 296 const unsigned Config_K23_HI = 30; 297 const unsigned Config_K23_LO = 28; 298 const unsigned Config_KU_HI = 27; 299 const unsigned Config_KU_LO = 25; 300 const unsigned Config_IMPL_HI = 24; 301 const unsigned Config_IMPL_LO = 16; 302 const unsigned Config_BE_HI = 15; 303 const unsigned Config_BE_LO = 15; 304 const unsigned Config_AT_HI = 14; 305 const unsigned Config_AT_LO = 13; 306 const unsigned Config_AR_HI = 12; 307 const unsigned Config_AR_LO = 10; 308 const unsigned Config_MT_HI = 9; 309 const unsigned Config_MT_LO = 7; 310 const unsigned Config_VI_HI = 3; 311 const unsigned Config_VI_LO = 3; 312 const unsigned Config_K0_HI = 2; 313 const unsigned Config_K0_LO = 0; 314 315 // Config1 Register - CP0 Reg 16, Sel 1 316 const unsigned Config1_M = 31; 317 const unsigned Config1_MMUSize_HI = 30; 318 const unsigned Config1_MMUSize_LO = 25; 319 const unsigned Config1_IS_HI = 24; 320 const unsigned Config1_IS_LO = 22; 321 const unsigned Config1_IL_HI = 21; 322 const unsigned Config1_IL_LO = 19; 323 const unsigned Config1_IA_HI = 18; 324 const unsigned Config1_IA_LO = 16; 325 const unsigned Config1_DS_HI = 15; 326 const unsigned Config1_DS_LO = 13; 327 const unsigned Config1_DL_HI = 12; 328 const unsigned Config1_DL_LO = 10; 329 const unsigned Config1_DA_HI = 9; 330 const unsigned Config1_DA_LO = 7; 331 const unsigned Config1_C2_HI = 6; 332 const unsigned Config1_C2_LO = 6; 333 const unsigned Config1_MD_HI = 5; 334 const unsigned Config1_MD_LO = 5; 335 const unsigned Config1_PC_HI = 4; 336 const unsigned Config1_PC_LO = 4; 337 const unsigned Config1_WR_HI = 3; 338 const unsigned Config1_WR_LO = 3; 339 const unsigned Config1_CA_HI = 2; 340 const unsigned Config1_CA_LO = 2; 341 const unsigned Config1_EP_HI = 1; 342 const unsigned Config1_EP_LO = 1; 343 const unsigned Config1_FP_HI = 0; 344 const unsigned Config1_FP_LO = 0; 345 346 347 // Config2 Register - CP0 Reg 16, Sel 2 348 const unsigned Config2_M = 31; 349 const unsigned Config2_TU_HI = 30; 350 const unsigned Config2_TU_LO = 28; 351 const unsigned Config2_TS_HI = 27; 352 const unsigned Config2_TS_LO = 24; 353 const unsigned Config2_TL_HI = 23; 354 const unsigned Config2_TL_LO = 20; 355 const unsigned Config2_TA_HI = 19; 356 const unsigned Config2_TA_LO = 16; 357 const unsigned Config2_SU_HI = 15; 358 const unsigned Config2_SU_LO = 12; 359 const unsigned Config2_SS_HI = 11; 360 const unsigned Config2_SS_LO = 8; 361 const unsigned Config2_SL_HI = 7; 362 const unsigned Config2_SL_LO = 4; 363 const unsigned Config2_SA_HI = 3; 364 const unsigned Config2_SA_LO = 0; 365 366 // Config3 Register - CP0 Reg 16, Sel 3 367 const unsigned Config3_M = 31; 368 const unsigned Config3_DSPP_HI = 10; 369 const unsigned Config3_DSPP_LO = 10; 370 const unsigned Config3_LPA_HI=7; 371 const unsigned Config3_LPA_LO=7; 372 const unsigned Config3_VEIC_HI=6; 373 const unsigned Config3_VEIC_LO=6; 374 const unsigned Config3_VINT_HI=5; 375 const unsigned Config3_VINT_LO=5; 376 const unsigned Config3_SP=4; 377 const unsigned Config3_SP_HI=4; 378 const unsigned Config3_SP_LO=4; 379 const unsigned Config3_MT_HI=2; 380 const unsigned Config3_MT_LO=2; 381 const unsigned Config3_SM_HI=1; 382 const unsigned Config3_SM_LO=1; 383 const unsigned Config3_TL_HI=0; 384 const unsigned Config3_TL_LO=0; 385 386 387 // LLAddr Register - CP0 Reg 17, Sel 0 388 // Load Linked Address (Physical) 389 const unsigned LLAddr_PAddr_HI = 31; 390 const unsigned LLAddr_PAddr_LO = 0; 391 392 393 394 // WatchLo Register - CP0 Reg 18, Sel 0-n 395 // See WatchHi to determine how many pairs of these registers are available 396 const unsigned WatchLo_VAddr_HI = 31; 397 const unsigned WatchLo_VAddr_LO = 3; 398 const unsigned WatchLo_I = 2; 399 const unsigned WatchLo_R = 1; 400 const unsigned WatchLo_W = 0; 401 402 403 // WatchHi Register - CP0 Reg 19, Sel 0-n 404 const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist 405 const unsigned WatchHi_G = 30; 406 const unsigned WatchHi_ASID_HI = 23; 407 const unsigned WatchHi_ASID_LO = 16; 408 const unsigned WatchHi_Mask_HI = 11; 409 const unsigned WatchHi_Mask_LO = 3; 410 const unsigned WatchHi_I = 2; 411 const unsigned WatchHi_R = 1; 412 const unsigned WatchHi_W = 0; 413 414 // Debug Register - CP0 Reg 23, Sel 0 415 416 // TraceControl Register - CP0 Reg 23, Sel 1 417 // TraceControl2 Register - CP0 Reg 23, Sel 2 418 // UserTraceData Register - CP0 Reg 23, Sel 3 419 // TraceBPC Register - CP0 Reg 23, Sel 4 420 // DEPC Register - CP0 Reg 24, Sel 0 421 422 423 // PerfCnt Register - CP0 Reg 25, Sel 0-n 424 // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25 425 // Even values are control registers, odd values are the actual counter 426 // The format for the control reg is: 427 const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers? 428 const unsigned PerfCntCtl_W = 30; 429 const unsigned PerfCntCtl_Event_HI = 10; 430 const unsigned PerfCntCtl_Event_LO = 5; 431 const unsigned PerfCntCtl_IE = 4; 432 const unsigned PerfCntCtl_U = 3; 433 const unsigned PerfCntCtl_S = 2; 434 const unsigned PerfCntCtl_K = 1; 435 const unsigned PerfCntCtl_EXL = 0; 436 437 // The format for the counter is a 32-bit value (or 64-bit for MIPS64) 438 const unsigned PerfCnt_Count_HI = 31; 439 const unsigned PerfCnt_Count_LO = 0; 440 441 // ErrCtl Register - CP0 Reg 26, Sel 0 442 // This is implementation dependent, not defined by the ISA 443 444 // CacheErr Register - CP0 Reg 27, Sel 0 445 // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3) 446 // used by the CacheErr registers. However, on page 134, only one sel value is shown 447 const unsigned Cache_Err_ER = 31; 448 const unsigned Cache_Err_EC = 30; 449 const unsigned Cache_Err_ED = 29; 450 const unsigned Cache_Err_ET = 28; 451 const unsigned Cache_Err_ES = 27; 452 const unsigned Cache_Err_EE = 26; 453 const unsigned Cache_Err_EB = 25; 454 const unsigned Cache_Err_IMPL_HI = 24; 455 const unsigned Cache_Err_IMPL_LO = 22; 456 const unsigned Cache_Err_Index_HI = 21; 457 const unsigned Cache_Err_Index_LO = 0; 458 459 // TagLo Register - CP0 Reg 28 - Even Selects (0,2) 460 const unsigned TagLo_PTagLo_HI = 31; 461 const unsigned TagLo_PTagLo_LO = 8; 462 const unsigned TagLo_PState_HI = 7; 463 const unsigned TagLo_PState_LO = 6; 464 const unsigned TagLo_L = 5; 465 const unsigned TagLo_IMPL_HI = 4; 466 const unsigned TagLo_IMPL_LO = 3; 467 const unsigned TagLo_P = 0; 468 // undefined bits must be written 0 469 470 471 // DataLo Register - CP0 Reg 28 - Odd Selects (1,3) 472 const unsigned DataLo_HI = 31; 473 const unsigned DataLo_LO = 0; 474 475 // TagHi Register - CP0 Reg 29 - Even Selects (0,2) 476 // Not defined by the architecture 477 478 // DataHi Register - CP0 Reg 29 - Odd Selects (1,3) 479 const unsigned DataHi_HI = 31; 480 const unsigned DataHi_LO = 0; 481 482 483 // ErrorEPC - CP0 Reg 30, Sel 0 484 const unsigned ErrorPC_HI = 31; 485 const unsigned ErrorPC_LO = 0; 486 487 // DESAVE - CP0 Reg 31, Sel 0 488 489 490 491 492 | |
493} // namespace MipsISA 494 495#endif | 324} // namespace MipsISA 325 326#endif |