1/* 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Korey Sewell 29 * Jaidev Patwardhan 30 */ 31 32#ifndef __ARCH_MIPS_MT_CONSTANTS_HH__ 33#define __ARCH_MIPS_MT_CONSTANTS_HH__ 34 35#include "arch/mips/types.hh" |
36#include "base/bitunion.hh" |
37 38namespace MipsISA 39{ |
40 |
41BitUnion32(MVPControlReg) 42 Bitfield<3> cpa; 43 Bitfield<2> stlb; 44 Bitfield<1> vpc; 45 Bitfield<0> evp; 46EndBitUnion(MVPControlReg) |
47 |
48BitUnion32(MVPConf0Reg) 49 Bitfield<31> m; 50 Bitfield<29> tlbs; 51 Bitfield<28> gs; 52 Bitfield<27> pcp; 53 Bitfield<25, 16> ptlbe; 54 Bitfield<15> tca; 55 Bitfield<13, 10> pvpe; 56 Bitfield<7, 0> ptc; 57EndBitUnion(MVPConf0Reg) |
58 |
59BitUnion32(VPEControlReg) 60 Bitfield<21> ysi; 61 Bitfield<18, 16> excpt; 62 Bitfield<15> te; 63 Bitfield<7, 0> targTC; 64EndBitUnion(VPEControlReg) |
65 |
66BitUnion32(VPEConf0Reg) 67 Bitfield<31> m; 68 Bitfield<28, 21> xtc; 69 Bitfield<19> tcs; 70 Bitfield<18> scs; 71 Bitfield<17> dcs; 72 Bitfield<16> ics; 73 Bitfield<1> mvp; 74 Bitfield<0> vpa; 75EndBitUnion(VPEConf0Reg) |
76 |
77BitUnion32(TCBindReg) 78 Bitfield<28, 21> curTC; 79 Bitfield<20, 18> a0; 80 Bitfield<17> tbe; 81 Bitfield<3, 0> curVPE; 82EndBitUnion(TCBindReg) |
83 |
84BitUnion32(TCStatusReg) 85 Bitfield<31, 28> tcu; 86 Bitfield<27> tmx; 87 Bitfield<24, 23> rnst; 88 Bitfield<21> tds; 89 Bitfield<20> dt; 90 Bitfield<19, 16> impl; 91 Bitfield<15> da; 92 Bitfield<13> a; 93 Bitfield<12, 11> tksu; 94 Bitfield<10> ixmt; 95 Bitfield<7, 0> asid; 96EndBitUnion(TCStatusReg) |
97 |
98BitUnion32(TCHaltReg) 99 Bitfield<0> h; 100EndBitUnion(TCHaltReg) |
101 |
102} // namespace MipsISA 103 104#endif |