locked_mem.hh (8232:b28d06a175be) locked_mem.hh (9383:55fa95053ee8)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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36 *
37 * ISA-specific helper functions for locked memory accesses.
38 */
39
40#include "arch/registers.hh"
41#include "base/misc.hh"
42#include "base/trace.hh"
43#include "debug/LLSC.hh"
14 * Copyright (c) 2006-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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48 *
49 * ISA-specific helper functions for locked memory accesses.
50 */
51
52#include "arch/registers.hh"
53#include "base/misc.hh"
54#include "base/trace.hh"
55#include "debug/LLSC.hh"
56#include "mem/packet.hh"
44#include "mem/request.hh"
45
46namespace MipsISA
47{
57#include "mem/request.hh"
58
59namespace MipsISA
60{
61template <class XC>
62inline void
63handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
64{
65 if (!xc->readMiscReg(MISCREG_LLFLAG))
66 return;
48
67
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
69 Addr snoop_addr = pkt->getAddr();
70
71 assert((cacheBlockMask & snoop_addr) == snoop_addr);
72
73 if (locked_addr == snoop_addr)
74 xc->setMiscReg(MISCREG_LLFLAG, false);
75}
76
77
49template <class XC>
50inline void
51handleLockedRead(XC *xc, Request *req)
52{
53 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
54 xc->setMiscReg(MISCREG_LLFLAG, true);
55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
56 " Address set to %x.\n",

--- 55 unchanged lines hidden --- 		78template <class XC>
79inline void
80handleLockedRead(XC *xc, Request *req)
81{
82 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
83 xc->setMiscReg(MISCREG_LLFLAG, true);
84 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
85 " Address set to %x.\n",

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