locked_mem.hh (7676:92274350b953) locked_mem.hh (7783:9b880b40ac10)
1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44
45namespace MipsISA
46{
47
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44
45namespace MipsISA
46{
47
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52 xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
53 xc->setMiscRegNoEffect(MISCREG_LLFLAG, true);
52 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
53 xc->setMiscReg(MISCREG_LLFLAG, true);
54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
55 " Address set to %x.\n",
56 req->threadId(), req->getPaddr() & ~0xf);
57}
58
59template <class XC>
60inline bool
61handleLockedWrite(XC *xc, Request *req)
62{
63 if (req->isUncacheable()) {
64 // Funky Turbolaser mailbox access...don't update
65 // result register (see stq_c in decoder.isa)
66 req->setExtraData(2);
67 } else {
68 // standard store conditional
54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
55 " Address set to %x.\n",
56 req->threadId(), req->getPaddr() & ~0xf);
57}
58
59template <class XC>
60inline bool
61handleLockedWrite(XC *xc, Request *req)
62{
63 if (req->isUncacheable()) {
64 // Funky Turbolaser mailbox access...don't update
65 // result register (see stq_c in decoder.isa)
66 req->setExtraData(2);
67 } else {
68 // standard store conditional
69 bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG);
70 Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR);
69 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
70 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
71
72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
73 // Lock flag not set or addr mismatch in CPU;
74 // don't even bother sending to memory system
75 req->setExtraData(0);
71
72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
73 // Lock flag not set or addr mismatch in CPU;
74 // don't even bother sending to memory system
75 req->setExtraData(0);
76 xc->setMiscRegNoEffect(MISCREG_LLFLAG, false);
76 xc->setMiscReg(MISCREG_LLFLAG, false);
77
78 // the rest of this code is not architectural;
79 // it's just a debugging aid to help detect
80 // livelock by warning on long sequences of failed
81 // store conditionals
82 int stCondFailures = xc->readStCondFailures();
83 stCondFailures++;
84 xc->setStCondFailures(stCondFailures);

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78 // the rest of this code is not architectural;
79 // it's just a debugging aid to help detect
80 // livelock by warning on long sequences of failed
81 // store conditionals
82 int stCondFailures = xc->readStCondFailures();
83 stCondFailures++;
84 xc->setStCondFailures(stCondFailures);

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