locked_mem.hh (6383:31c067ae3331) locked_mem.hh (6425:ed56e2cac9aa)
1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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46namespace MipsISA
47{
48
49template <class XC>
50inline void
51handleLockedRead(XC *xc, Request *req)
52{
53 xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 37 unchanged lines hidden (view full) ---

46namespace MipsISA
47{
48
49template <class XC>
50inline void
51handleLockedRead(XC *xc, Request *req)
52{
53 xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
54 xc->setMiscRegNoEffect(MISCREG_LLADDR, true);
54 xc->setMiscRegNoEffect(MISCREG_LLFLAG, true);
55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
56 " Address set to %x.\n",
57 req->threadId(), req->getPaddr() & ~0xf);
58}
59
60template <class XC>
61inline bool
62handleLockedWrite(XC *xc, Request *req)

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78
79 // the rest of this code is not architectural;
80 // it's just a debugging aid to help detect
81 // livelock by warning on long sequences of failed
82 // store conditionals
83 int stCondFailures = xc->readStCondFailures();
84 stCondFailures++;
85 xc->setStCondFailures(stCondFailures);
55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
56 " Address set to %x.\n",
57 req->threadId(), req->getPaddr() & ~0xf);
58}
59
60template <class XC>
61inline bool
62handleLockedWrite(XC *xc, Request *req)

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78
79 // the rest of this code is not architectural;
80 // it's just a debugging aid to help detect
81 // livelock by warning on long sequences of failed
82 // store conditionals
83 int stCondFailures = xc->readStCondFailures();
84 stCondFailures++;
85 xc->setStCondFailures(stCondFailures);
86 if (stCondFailures % 10 == 0) {
86 if (stCondFailures % 100000 == 0) {
87 warn("%i: context %d: %d consecutive "
88 "store conditional failures\n",
89 curTick, xc->contextId(), stCondFailures);
90 }
91
87 warn("%i: context %d: %d consecutive "
88 "store conditional failures\n",
89 curTick, xc->contextId(), stCondFailures);
90 }
91
92 if (stCondFailures == 5000) {
93 panic("Max (5000) Store Conditional Fails Reached. "
94 "Check Code For Deadlock.\n");
95 }
96
97 if (!lock_flag){
98 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
99 "Store Conditional Failed.\n",
100 req->threadId());
101 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
102 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
103 "Store Conditional Failed.\n",
104 req->threadId());

--- 12 unchanged lines hidden --- 		92 if (!lock_flag){
93 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
94 "Store Conditional Failed.\n",
95 req->threadId());
96 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
97 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
98 "Store Conditional Failed.\n",
99 req->threadId());

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