locked_mem.hh (5254:c555f8b07345) | locked_mem.hh (5596:cdc8893c649e) |
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1/* 2 * Copyright (c) 2006-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44 45 46namespace MipsISA 47{ 48template <class XC> 49inline void 50handleLockedRead(XC *xc, Request *req) 51{ | 1/* 2 * Copyright (c) 2006-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44 45 46namespace MipsISA 47{ 48template <class XC> 49inline void 50handleLockedRead(XC *xc, Request *req) 51{ |
52 unsigned tid = req->getThreadNum(); 53 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid); 54 xc->setMiscRegNoEffect(LLFlag, true, tid); | 52 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); 53 xc->setMiscRegNoEffect(LLFlag, true); |
55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", | 54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", |
56 tid, req->getPaddr() & ~0xf); | 55 req->getThreadNum(), req->getPaddr() & ~0xf); |
57} 58 59 60template <class XC> 61inline bool 62handleLockedWrite(XC *xc, Request *req) 63{ | 56} 57 58 59template <class XC> 60inline bool 61handleLockedWrite(XC *xc, Request *req) 62{ |
64 unsigned tid = req->getThreadNum(); 65 | |
66 if (req->isUncacheable()) { 67 // Funky Turbolaser mailbox access...don't update 68 // result register (see stq_c in decoder.isa) 69 req->setExtraData(2); 70 } else { 71 // standard store conditional | 63 if (req->isUncacheable()) { 64 // Funky Turbolaser mailbox access...don't update 65 // result register (see stq_c in decoder.isa) 66 req->setExtraData(2); 67 } else { 68 // standard store conditional |
72 bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid); 73 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid); | 69 bool lock_flag = xc->readMiscRegNoEffect(LLFlag); 70 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); |
74 75 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 76 // Lock flag not set or addr mismatch in CPU; 77 // don't even bother sending to memory system 78 req->setExtraData(0); | 71 72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 73 // Lock flag not set or addr mismatch in CPU; 74 // don't even bother sending to memory system 75 req->setExtraData(0); |
79 xc->setMiscRegNoEffect(LLFlag, false, tid); | 76 xc->setMiscRegNoEffect(LLFlag, false); |
80 81 // the rest of this code is not architectural; 82 // it's just a debugging aid to help detect 83 // livelock by warning on long sequences of failed 84 // store conditionals 85 int stCondFailures = xc->readStCondFailures(); 86 stCondFailures++; 87 xc->setStCondFailures(stCondFailures); --- 4 unchanged lines hidden (view full) --- 92 } 93 94 if (stCondFailures == 5000) { 95 panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); 96 } 97 98 if (!lock_flag){ 99 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", | 77 78 // the rest of this code is not architectural; 79 // it's just a debugging aid to help detect 80 // livelock by warning on long sequences of failed 81 // store conditionals 82 int stCondFailures = xc->readStCondFailures(); 83 stCondFailures++; 84 xc->setStCondFailures(stCondFailures); --- 4 unchanged lines hidden (view full) --- 89 } 90 91 if (stCondFailures == 5000) { 92 panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); 93 } 94 95 if (!lock_flag){ 96 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", |
100 tid); | 97 req->getThreadNum()); |
101 } else if ((req->getPaddr() & ~0xf) != lock_addr) { 102 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", | 98 } else if ((req->getPaddr() & ~0xf) != lock_addr) { 99 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", |
103 tid); | 100 req->getThreadNum()); |
104 } 105 // store conditional failed already, so don't issue it to mem 106 return false; 107 } 108 } 109 110 return true; 111} 112 113 114} // namespace MipsISA 115 116#endif | 101 } 102 // store conditional failed already, so don't issue it to mem 103 return false; 104 } 105 } 106 107 return true; 108} 109 110 111} // namespace MipsISA 112 113#endif |