locked_mem.hh (4661:44458219add1) locked_mem.hh (5222:bb733a878f85)
1/*
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
2 * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
4 *
3 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
4 * This software is part of the M5 simulator.
15 *
5 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.
27 *
9 *
28 * Authors: Steve Reinhardt
10 * Permission is granted to use, copy, create derivative works and
11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
21 * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
33 *
34 * Authors: Steven K. Reinhardt
29 */
30
31#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
32#define __ARCH_MIPS_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *

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45
46namespace MipsISA
47{
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52 unsigned tid = req->getThreadNum();
35 */
36
37#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
38#define __ARCH_MIPS_LOCKED_MEM_HH__
39
40/**
41 * @file
42 *

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51
52namespace MipsISA
53{
54template <class XC>
55inline void
56handleLockedRead(XC *xc, Request *req)
57{
58 unsigned tid = req->getThreadNum();
53 xc->setMiscReg(LLAddr, req->getPaddr() & ~0xf, tid);
54 xc->setMiscReg(LLFlag, true, tid);
59 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid);
60 xc->setMiscRegNoEffect(LLFlag, true, tid);
55 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
56 tid, req->getPaddr() & ~0xf);
57}
58
59
60template <class XC>
61inline bool
62handleLockedWrite(XC *xc, Request *req)
63{
64 unsigned tid = req->getThreadNum();
65
66 if (req->isUncacheable()) {
67 // Funky Turbolaser mailbox access...don't update
68 // result register (see stq_c in decoder.isa)
69 req->setExtraData(2);
70 } else {
71 // standard store conditional
61 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
62 tid, req->getPaddr() & ~0xf);
63}
64
65
66template <class XC>
67inline bool
68handleLockedWrite(XC *xc, Request *req)
69{
70 unsigned tid = req->getThreadNum();
71
72 if (req->isUncacheable()) {
73 // Funky Turbolaser mailbox access...don't update
74 // result register (see stq_c in decoder.isa)
75 req->setExtraData(2);
76 } else {
77 // standard store conditional
72 bool lock_flag = xc->readMiscReg(LLFlag, tid);
73 Addr lock_addr = xc->readMiscReg(LLAddr, tid);
78 bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid);
79 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid);
74
75 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
76 // Lock flag not set or addr mismatch in CPU;
77 // don't even bother sending to memory system
78 req->setExtraData(0);
80
81 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
82 // Lock flag not set or addr mismatch in CPU;
83 // don't even bother sending to memory system
84 req->setExtraData(0);
79 xc->setMiscReg(LLFlag, false, tid);
85 xc->setMiscRegNoEffect(LLFlag, false, tid);
80
81 // the rest of this code is not architectural;
82 // it's just a debugging aid to help detect
83 // livelock by warning on long sequences of failed
84 // store conditionals
85 int stCondFailures = xc->readStCondFailures();
86 stCondFailures++;
87 xc->setStCondFailures(stCondFailures);

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87 // the rest of this code is not architectural;
88 // it's just a debugging aid to help detect
89 // livelock by warning on long sequences of failed
90 // store conditionals
91 int stCondFailures = xc->readStCondFailures();
92 stCondFailures++;
93 xc->setStCondFailures(stCondFailures);

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