locked_mem.hh (12748:ae5ce8e42de7) locked_mem.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 61 unchanged lines hidden (view full) ---

70
71 if (locked_addr == snoop_addr)
72 xc->setMiscReg(MISCREG_LLFLAG, false);
73}
74
75
76template <class XC>
77inline void
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 61 unchanged lines hidden (view full) ---

70
71 if (locked_addr == snoop_addr)
72 xc->setMiscReg(MISCREG_LLFLAG, false);
73}
74
75
76template <class XC>
77inline void
78handleLockedRead(XC *xc, RequestPtr req)
78handleLockedRead(XC *xc, const RequestPtr &req)
79{
80 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
81 xc->setMiscReg(MISCREG_LLFLAG, true);
82 DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
83 " Address set to %x.\n",
84 req->contextId(), req->getPaddr() & ~0xf);
85}
86
87template <class XC>
88inline void
89handleLockedSnoopHit(XC *xc)
90{
91}
92
93template <class XC>
94inline bool
79{
80 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
81 xc->setMiscReg(MISCREG_LLFLAG, true);
82 DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link"
83 " Address set to %x.\n",
84 req->contextId(), req->getPaddr() & ~0xf);
85}
86
87template <class XC>
88inline void
89handleLockedSnoopHit(XC *xc)
90{
91}
92
93template <class XC>
94inline bool
95handleLockedWrite(XC *xc, RequestPtr req, Addr cacheBlockMask)
95handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
96{
97 if (req->isUncacheable()) {
98 // Funky Turbolaser mailbox access...don't update
99 // result register (see stq_c in decoder.isa)
100 req->setExtraData(2);
101 } else {
102 // standard store conditional
103 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);

--- 48 unchanged lines hidden --- 		96{
97 if (req->isUncacheable()) {
98 // Funky Turbolaser mailbox access...don't update
99 // result register (see stq_c in decoder.isa)
100 req->setExtraData(2);
101 } else {
102 // standard store conditional
103 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);

--- 48 unchanged lines hidden ---