1/* |
2 * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved |
3 * |
4 * This software is part of the M5 simulator. |
5 * |
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 8 * TO THESE TERMS AND CONDITIONS. |
9 * |
10 * Permission is granted to use, copy, create derivative works and 11 * distribute this software and such derivative works for any purpose, 12 * so long as (1) the copyright notice above, this grant of permission, 13 * and the disclaimer below appear in all copies and derivative works 14 * made, (2) the copyright notice above is augmented as appropriate to 15 * reflect the addition of any new copyrightable work in a derivative 16 * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 17 * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 18 * advertising or publicity pertaining to the use or distribution of 19 * this software without specific, written prior authorization. 20 * 21 * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 33 * 34 * Authors: Steven K. Reinhardt |
35 */ 36 37#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 38#define __ARCH_MIPS_LOCKED_MEM_HH__ 39 40/** 41 * @file 42 * --- 8 unchanged lines hidden (view full) --- 51 52namespace MipsISA 53{ 54template <class XC> 55inline void 56handleLockedRead(XC *xc, Request *req) 57{ 58 unsigned tid = req->getThreadNum(); |
59 xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid); 60 xc->setMiscRegNoEffect(LLFlag, true, tid); |
61 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", 62 tid, req->getPaddr() & ~0xf); 63} 64 65 66template <class XC> 67inline bool 68handleLockedWrite(XC *xc, Request *req) 69{ 70 unsigned tid = req->getThreadNum(); 71 72 if (req->isUncacheable()) { 73 // Funky Turbolaser mailbox access...don't update 74 // result register (see stq_c in decoder.isa) 75 req->setExtraData(2); 76 } else { 77 // standard store conditional |
78 bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid); 79 Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid); |
80 81 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 82 // Lock flag not set or addr mismatch in CPU; 83 // don't even bother sending to memory system 84 req->setExtraData(0); |
85 xc->setMiscRegNoEffect(LLFlag, false, tid); |
86 87 // the rest of this code is not architectural; 88 // it's just a debugging aid to help detect 89 // livelock by warning on long sequences of failed 90 // store conditionals 91 int stCondFailures = xc->readStCondFailures(); 92 stCondFailures++; 93 xc->setStCondFailures(stCondFailures); --- 29 unchanged lines hidden --- |