1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
32#define __ARCH_MIPS_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 */
39
40#include "arch/registers.hh"
41#include "base/misc.hh"
42#include "base/trace.hh"
43#include "mem/request.hh"
44
45namespace MipsISA
46{
47
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
53 xc->setMiscReg(MISCREG_LLFLAG, true);
54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
55 " Address set to %x.\n",
56 req->threadId(), req->getPaddr() & ~0xf);
57}
58
59template <class XC>
60inline bool
61handleLockedWrite(XC *xc, Request *req)
62{
63 if (req->isUncacheable()) {
64 // Funky Turbolaser mailbox access...don't update
65 // result register (see stq_c in decoder.isa)
66 req->setExtraData(2);
67 } else {
68 // standard store conditional
69 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
70 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
71
72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
73 // Lock flag not set or addr mismatch in CPU;
74 // don't even bother sending to memory system
75 req->setExtraData(0);
76 xc->setMiscReg(MISCREG_LLFLAG, false);
77
78 // the rest of this code is not architectural;
79 // it's just a debugging aid to help detect
80 // livelock by warning on long sequences of failed
81 // store conditionals
82 int stCondFailures = xc->readStCondFailures();
83 stCondFailures++;
84 xc->setStCondFailures(stCondFailures);
85 if (stCondFailures % 100000 == 0) {
86 warn("%i: context %d: %d consecutive "
87 "store conditional failures\n",
| 1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
32#define __ARCH_MIPS_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 */
39
40#include "arch/registers.hh"
41#include "base/misc.hh"
42#include "base/trace.hh"
43#include "mem/request.hh"
44
45namespace MipsISA
46{
47
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52 xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
53 xc->setMiscReg(MISCREG_LLFLAG, true);
54 DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
55 " Address set to %x.\n",
56 req->threadId(), req->getPaddr() & ~0xf);
57}
58
59template <class XC>
60inline bool
61handleLockedWrite(XC *xc, Request *req)
62{
63 if (req->isUncacheable()) {
64 // Funky Turbolaser mailbox access...don't update
65 // result register (see stq_c in decoder.isa)
66 req->setExtraData(2);
67 } else {
68 // standard store conditional
69 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
70 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
71
72 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
73 // Lock flag not set or addr mismatch in CPU;
74 // don't even bother sending to memory system
75 req->setExtraData(0);
76 xc->setMiscReg(MISCREG_LLFLAG, false);
77
78 // the rest of this code is not architectural;
79 // it's just a debugging aid to help detect
80 // livelock by warning on long sequences of failed
81 // store conditionals
82 int stCondFailures = xc->readStCondFailures();
83 stCondFailures++;
84 xc->setStCondFailures(stCondFailures);
85 if (stCondFailures % 100000 == 0) {
86 warn("%i: context %d: %d consecutive "
87 "store conditional failures\n",
|
89 }
90
91 if (!lock_flag){
92 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
93 "Store Conditional Failed.\n",
94 req->threadId());
95 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
96 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
97 "Store Conditional Failed.\n",
98 req->threadId());
99 }
100 // store conditional failed already, so don't issue it to mem
101 return false;
102 }
103 }
104
105 return true;
106}
107
108} // namespace MipsISA
109
110#endif
| 89 }
90
91 if (!lock_flag){
92 DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
93 "Store Conditional Failed.\n",
94 req->threadId());
95 } else if ((req->getPaddr() & ~0xf) != lock_addr) {
96 DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
97 "Store Conditional Failed.\n",
98 req->threadId());
99 }
100 // store conditional failed already, so don't issue it to mem
101 return false;
102 }
103 }
104
105 return true;
106}
107
108} // namespace MipsISA
109
110#endif
|