operands.isa (6383:31c067ae3331) operands.isa (6807:14fbdb0f9585)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
111
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 95 unchanged lines hidden (view full) ---

104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
111
112 #Thread pointer value for SE mode
113 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
114
112 # Index Register
115 # Index Register
113 'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
116 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
114
115
116 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
117
118 #MT Control Regs
119 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
120 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
121 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),

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118
119 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
120
121 #MT Control Regs
122 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
123 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
124 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),

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