operands.isa (6376:eaf61ef6a8f2) operands.isa (6383:31c067ae3331)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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51 #Immediate Value operand
52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
53
54 #Operands used for Link or Syscall Insts
55 'R31': ('IntReg', 'uw','31','IsInteger', 4),
56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
57
58 #Special Integer Reg operands
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 42 unchanged lines hidden (view full) ---

51 #Immediate Value operand
52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
53
54 #Operands used for Link or Syscall Insts
55 'R31': ('IntReg', 'uw','31','IsInteger', 4),
56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
57
58 #Special Integer Reg operands
59 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
60 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
59 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
60 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
61
62 #Bitfield-dependent HI/LO Register Access
61
62 #Bitfield-dependent HI/LO Register Access
63 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
64 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
65 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
66 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
63 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
64 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
65 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
66 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
67
68 #DSP Special Purpose Integer Operands
67
68 #DSP Special Purpose Integer Operands
69 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
70 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
71 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
72 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
73 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
74 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
75 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
76 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
77 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
78 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
79 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
80 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
81 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
69 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
70 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
71 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
72 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
73 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
74 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
75 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
76 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
77 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
78 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
79 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
80 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
81 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
82
83 #Floating Point Reg Operands
84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
88
89 #Special Purpose Floating Point Control Reg Operands
82
83 #Floating Point Reg Operands
84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
88
89 #Special Purpose Floating Point Control Reg Operands
90 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
91 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
92 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
93 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
94 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
90 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
91 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
92 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
93 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
94 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
95
96 #Operands For Paired Singles FP Operations
97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
95
96 #Operands For Paired Singles FP Operations
97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
107 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
108
109 #LL Flag
108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
110 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
111
112 # Index Register
111
112 # Index Register
113 'Index':('ControlReg','uw','MipsISA::Index',None,1),
113 'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
114
115
116 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
117
118 #MT Control Regs
114
115
116 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
117
118 #MT Control Regs
119 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
120 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
121 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
122 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
123 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
124 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
125 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
126 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
119 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
120 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
121 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
122 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
123 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
124 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
125 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
126 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
127
128 #CP0 Control Regs
127
128 #CP0 Control Regs
129 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
130 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
131 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
132 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
133 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
134 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
135 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
136 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
137 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
138 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
139 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
140 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
141 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
142 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
143 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1),
144 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
129 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
130 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
131 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
132 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
133 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
134 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
135 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
136 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
137 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
138 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
139 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
140 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
141 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
142 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
143 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
144 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
145 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
145
146 #Memory Operand
147 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
148
149 #Program Counter Operands
150 'NPC': ('NPC', 'uw', None, 'IsControl', 4),
151 'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
152}};
146
147 #Memory Operand
148 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
149
150 #Program Counter Operands
151 'NPC': ('NPC', 'uw', None, 'IsControl', 4),
152 'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
153}};