Cross Reference: /gem5/src/arch/mips/isa/operands.isa

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operands.isa (6338:14572c7334b5)	operands.isa (6376:eaf61ef6a8f2)
1// -- mode:c++ -- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 126 unchanged lines hidden (view full) --- 135 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), 136 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), 137 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), 138 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), 139 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), 140 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), 141 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), 142 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),	1// -- mode:c++ -- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 126 unchanged lines hidden (view full) --- 135 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), 136 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), 137 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), 138 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), 139 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), 140 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), 141 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), 142 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
	143 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1), 144 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
143	145
144 145 # named bitfields of Control Regs 146 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 147 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 148 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 149 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 150 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 151 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 152 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 153 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 154 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 155 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 156 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 157 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), 158 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1), 159 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1), 160 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1), 161 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1), 162 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 163 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 164 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4), 165 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1), 166 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 167 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3), 168 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 169 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 170 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 171 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 172 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3), 173 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 174 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 175 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 176 177 # named bitfields of Debug Regs 178 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 179 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 180
181 #Memory Operand 182 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 183 184 #Program Counter Operands 185 'NPC': ('NPC', 'uw', None, 'IsControl', 4), 186 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) 187}};	146 #Memory Operand 147 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 148 149 #Program Counter Operands 150 'NPC': ('NPC', 'uw', None, 'IsControl', 4), 151 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) 152}};