operands.isa (5254:c555f8b07345) operands.isa (6338:14572c7334b5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
111
112 # Index Register
113 'Index':('ControlReg','uw','MipsISA::Index',None,1),
114
115
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
111
112 # Index Register
113 'Index':('ControlReg','uw','MipsISA::Index',None,1),
114
115
116 #Special cases for when a Control Register Access is dependent on
117 #a combination of bitfield indices (handles MTCO & MFCO)
118 # Fixed to allow CP0 Register Offset
119 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
116 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
120
121 #MT Control Regs
122 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
123 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
124 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
125 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
126 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
127 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),

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118 #MT Control Regs
119 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
120 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
121 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
122 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
123 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
124 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),

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