operands.isa (4661:44458219add1) | operands.isa (5222:bb733a878f85) |
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1// -*- mode:c++ -*- 2 | 1// -*- mode:c++ -*- 2 |
3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell | 3// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved |
30 | 4 |
5// This software is part of the M5 simulator. 6 7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 9// TO THESE TERMS AND CONDITIONS. 10 11// Permission is granted to use, copy, create derivative works and 12// distribute this software and such derivative works for any purpose, 13// so long as (1) the copyright notice above, this grant of permission, 14// and the disclaimer below appear in all copies and derivative works 15// made, (2) the copyright notice above is augmented as appropriate to 16// reflect the addition of any new copyrightable work in a derivative 17// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 18// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 19// advertising or publicity pertaining to the use or distribution of 20// this software without specific, written prior authorization. 21 22// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 34 35//Authors: Korey L. Sewell 36// Jaidev Patwardhan 37 |
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31def operand_types {{ 32 'sb' : ('signed int', 8), 33 'ub' : ('unsigned int', 8), 34 'sh' : ('signed int', 16), 35 'uh' : ('unsigned int', 16), 36 'sw' : ('signed int', 32), 37 'uw' : ('unsigned int', 32), 38 'sd' : ('signed int', 64), 39 'ud' : ('unsigned int', 64), 40 'sf' : ('float', 32), 41 'df' : ('float', 64), | 38def operand_types {{ 39 'sb' : ('signed int', 8), 40 'ub' : ('unsigned int', 8), 41 'sh' : ('signed int', 16), 42 'uh' : ('unsigned int', 16), 43 'sw' : ('signed int', 32), 44 'uw' : ('unsigned int', 32), 45 'sd' : ('signed int', 64), 46 'ud' : ('unsigned int', 64), 47 'sf' : ('float', 32), 48 'df' : ('float', 64), |
42 'qf' : ('float', 128) | |
43}}; 44 45def operands {{ 46 #General Purpose Integer Reg Operands 47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), 50 --- 50 unchanged lines hidden (view full) --- 101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), 102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), 103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), 104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), 105 106 #Status Control Reg 107 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), 108 | 49}}; 50 51def operands {{ 52 #General Purpose Integer Reg Operands 53 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 54 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 55 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), 56 --- 50 unchanged lines hidden (view full) --- 107 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), 108 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), 109 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), 110 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), 111 112 #Status Control Reg 113 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), 114 |
115 #LL Flag 116 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1), 117 118 # Index Register 119 'Index':('ControlReg','uw','MipsISA::Index',None,1), 120 121 |
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109 #Special cases for when a Control Register Access is dependent on 110 #a combination of bitfield indices (handles MTCO & MFCO) | 122 #Special cases for when a Control Register Access is dependent on 123 #a combination of bitfield indices (handles MTCO & MFCO) |
111 'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1), | 124 # Fixed to allow CP0 Register Offset 125 'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1), |
112 113 #MT Control Regs 114 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), 115 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), 116 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), 117 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), 118 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), 119 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), 120 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), 121 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), 122 | 126 127 #MT Control Regs 128 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), 129 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), 130 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), 131 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), 132 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), 133 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), 134 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), 135 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), 136 |
137 #CP0 Control Regs 138 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1), 139 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1), 140 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1), 141 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1), 142 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1), 143 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1), 144 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), 145 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), 146 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), 147 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), 148 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), 149 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), 150 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), 151 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), 152 153 |
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123 # named bitfields of Control Regs 124 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 125 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 126 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), | 154 # named bitfields of Control Regs 155 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 156 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 157 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), |
158 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), |
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127 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 128 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 129 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 130 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 131 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 132 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 133 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 134 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), | 159 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 160 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 161 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 162 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 163 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 164 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 165 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 166 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), |
167 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1), 168 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1), 169 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1), 170 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1), 171 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 172 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 173 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4), 174 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1), 175 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 176 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3), 177 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 178 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 179 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 180 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 181 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3), 182 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 183 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 184 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), |
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135 136 # named bitfields of Debug Regs 137 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 138 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 139 140 #Memory Operand 141 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 142 143 #Program Counter Operands 144 'NPC': ('NPC', 'uw', None, 'IsControl', 4), 145 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) 146}}; | 185 186 # named bitfields of Debug Regs 187 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 188 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 189 190 #Memory Operand 191 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 192 193 #Program Counter Operands 194 'NPC': ('NPC', 'uw', None, 'IsControl', 4), 195 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) 196}}; |