operands.isa (2754:e3d023bc752c) operands.isa (4661:44458219add1)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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43}};
44
45def operands {{
46 #General Purpose Integer Reg Operands
47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
50
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 34 unchanged lines hidden (view full) ---

43}};
44
45def operands {{
46 #General Purpose Integer Reg Operands
47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
50
51 #Immediate Value operand
52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
53
51 #Operands used for Link or Syscall Insts
52 'R31': ('IntReg', 'uw','31','IsInteger', 4),
53 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
54
55 #Special Integer Reg operands
54 #Operands used for Link or Syscall Insts
55 'R31': ('IntReg', 'uw','31','IsInteger', 4),
56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
57
58 #Special Integer Reg operands
56 'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
57 'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
59 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
60 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
58
61
59 #Immediate Value operand
60 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
62 #Bitfield-dependent HI/LO Register Access
63 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
64 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
65 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
66 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
61
67
68 #DSP Special Purpose Integer Operands
69 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
70 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
71 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
72 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
73 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
74 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
75 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
76 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
77 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
78 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
79 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
80 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
81 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
82
62 #Floating Point Reg Operands
63 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
64 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
65 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
66 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
67
83 #Floating Point Reg Operands
84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
88
68 #Special Floating Point Control Reg Operands
89 #Special Purpose Floating Point Control Reg Operands
69 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
70 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
71 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
72 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
73 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
74
90 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
91 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
92 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
93 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
94 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
95
75 #Operands For Paired Singles FP Operations
96 #Operands For Paired Singles FP Operations
76 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
77 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
78 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
79 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
80 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
81 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
82 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
83 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
84
97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
108
109 #Special cases for when a Control Register Access is dependent on
110 #a combination of bitfield indices (handles MTCO & MFCO)
111 'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1),
112
113 #MT Control Regs
114 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
115 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
116 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
117 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
118 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
119 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
120 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
121 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
122
123 # named bitfields of Control Regs
124 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
125 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
126 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
127 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
128 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
129 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
130 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
131 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
132 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
133 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
134 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
135
136 # named bitfields of Debug Regs
137 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
138 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
139
85 #Memory Operand
86 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
87
88 #Program Counter Operands
140 #Memory Operand
141 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
142
143 #Program Counter Operands
89 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
90 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
144 'NPC': ('NPC', 'uw', None, 'IsControl', 4),
145 'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
91}};
146}};