1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Jaidev Patwardhan
31
32def operand_types {{
33 'sb' : ('signed int', 8),
34 'ub' : ('unsigned int', 8),
35 'sh' : ('signed int', 16),
36 'uh' : ('unsigned int', 16),
37 'sw' : ('signed int', 32),
38 'uw' : ('unsigned int', 32),
39 'sd' : ('signed int', 64),
40 'ud' : ('unsigned int', 64),
41 'sf' : ('float', 32),
42 'df' : ('float', 64),
43}};
44
45def operands {{
46 #General Purpose Integer Reg Operands
47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
50
51 #Immediate Value operand
52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
53
54 #Operands used for Link or Syscall Insts
55 'R31': ('IntReg', 'uw','31','IsInteger', 4),
56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
57
58 #Special Integer Reg operands
59 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
60 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
61
62 #Bitfield-dependent HI/LO Register Access
63 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
64 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
65 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
66 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
67
68 #DSP Special Purpose Integer Operands
69 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
70 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
71 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
72 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
73 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
74 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
75 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
76 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
77 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
78 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
79 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
80 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
81 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
82
83 #Floating Point Reg Operands
84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
88
89 #Special Purpose Floating Point Control Reg Operands
90 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
91 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
92 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
93 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
94 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
95
96 #Operands For Paired Singles FP Operations
97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
111
112 #Thread pointer value for SE mode
113 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
114
115 # Index Register
116 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
117
118
119 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
120
121 #MT Control Regs
122 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
123 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
124 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
125 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
126 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
127 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
128 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
129 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
130
131 #CP0 Control Regs
132 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
133 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
134 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
135 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
136 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
137 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
138 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
139 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
140 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
141 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
142 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
143 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
144 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
145 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
146 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
147 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
148 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
149
150 #Memory Operand
151 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
152
153 #Program Counter Operands
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30// Jaidev Patwardhan
31
32def operand_types {{
33 'sb' : ('signed int', 8),
34 'ub' : ('unsigned int', 8),
35 'sh' : ('signed int', 16),
36 'uh' : ('unsigned int', 16),
37 'sw' : ('signed int', 32),
38 'uw' : ('unsigned int', 32),
39 'sd' : ('signed int', 64),
40 'ud' : ('unsigned int', 64),
41 'sf' : ('float', 32),
42 'df' : ('float', 64),
43}};
44
45def operands {{
46 #General Purpose Integer Reg Operands
47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
50
51 #Immediate Value operand
52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
53
54 #Operands used for Link or Syscall Insts
55 'R31': ('IntReg', 'uw','31','IsInteger', 4),
56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
57
58 #Special Integer Reg operands
59 'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
60 'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
61
62 #Bitfield-dependent HI/LO Register Access
63 'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
64 'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
65 'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
66 'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
67
68 #DSP Special Purpose Integer Operands
69 'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
70 'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
71 'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
72 'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
73 'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
74 'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
75 'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
76 'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
77 'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
78 'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
79 'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
80 'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
81 'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
82
83 #Floating Point Reg Operands
84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
88
89 #Special Purpose Floating Point Control Reg Operands
90 'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
91 'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
92 'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
93 'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
94 'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
95
96 #Operands For Paired Singles FP Operations
97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
105
106 #Status Control Reg
107 'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
108
109 #LL Flag
110 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
111
112 #Thread pointer value for SE mode
113 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
114
115 # Index Register
116 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
117
118
119 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
120
121 #MT Control Regs
122 'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
123 'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
124 'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
125 'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
126 'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
127 'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
128 'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
129 'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
130
131 #CP0 Control Regs
132 'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
133 'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
134 'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
135 'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
136 'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
137 'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
138 'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
139 'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
140 'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
141 'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
142 'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
143 'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
144 'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
145 'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
146 'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
147 'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
148 'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
149
150 #Memory Operand
151 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
152
153 #Program Counter Operands
|