1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'sh' : ('signed int', 16),
35 'uh' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'sd' : ('signed int', 64),
39 'ud' : ('unsigned int', 64),
40 'sf' : ('float', 32),
41 'df' : ('float', 64),
42 'qf' : ('float', 128)
43}};
44
45def operands {{
46 #General Purpose Integer Reg Operands
47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
50
51 #Operands used for Link or Syscall Insts
52 'R31': ('IntReg', 'uw','31','IsInteger', 4),
53 'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
54
55 #Special Integer Reg operands
56 'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
57 'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
58
59 #Immediate Value operand
60 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
61
62 #Floating Point Reg Operands
63 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
64 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
65 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
66 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
67
68 #Special Floating Point Control Reg Operands
69 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
70 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
71 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
72 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
73 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
74
75 #Operands For Paired Singles FP Operations
76 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
77 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
78 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
79 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
80 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
81 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
82 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
83 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
84
85 #Memory Operand
86 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
87
88 #Program Counter Operands
89 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
90 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
91}};