1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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135 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
136 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
137 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
138 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
139 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
140 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
141 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
142 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
143 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1),
144 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
145
146 #Memory Operand
147 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
148
149 #Program Counter Operands
150 'NPC': ('NPC', 'uw', None, 'IsControl', 4),
151 'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
152}};