1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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83 decode_template.subst(iop),
84 EACompExecute.subst(ea_iop)
85 + memAccExecTemplate.subst(memacc_iop)
86 + fullExecTemplate.subst(iop)
87 + initiateAccTemplate.subst(iop)
88 + completeAccTemplate.subst(iop))
89}};
90
91
92output header {{
93 std::string inst2string(MachInst machInst);
94}};
95
96output decoder {{
97
98std::string inst2string(MachInst machInst)
99{
100 std::string str = "";
101 uint32_t mask = 0x80000000;
102
103 for(int i=0; i < 32; i++) {
104 if ((machInst & mask) == 0) {
105 str += "0";
106 } else {
107 str += "1";
108 }
109
110 mask = mask >> 1;
111 }
112
113 return str;
114}
115
116}};
117output exec {{
118
119 using namespace MipsISA;
120
121 /// CLEAR ALL CPU INST/EXE HAZARDS
122 inline void
123 clear_exe_inst_hazards()
124 {
125 //CODE HERE
126 }
127
128
129 /// Check "FP enabled" machine status bit. Called when executing any FP
130 /// instruction in full-system mode.
131 /// @retval Full-system mode: NoFault if FP is enabled, FenFault
132 /// if not. Non-full-system mode: always returns NoFault.
133#if FULL_SYSTEM
134 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
135 {
136 Fault fault = NoFault; // dummy... this ipr access should not fault
137 if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
138 fault = FloatEnableFault;
139 }
140 return fault;
141 }
142#else
143 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
144 {
145 return NoFault;
146 }
147#endif
148
149
150
151}};
152
153