mt.isa (7823:dac01f14f20f) | mt.isa (8607:5fb918115c07) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 93 unchanged lines hidden (view full) --- 102 config3 = xc->readMiscReg(MISCREG_CONFIG3); 103 } 104}}; 105 106def template ThreadRegisterExecute {{ 107 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 108 { 109 Fault fault = NoFault; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 93 unchanged lines hidden (view full) --- 102 config3 = xc->readMiscReg(MISCREG_CONFIG3); 103 } 104}}; 105 106def template ThreadRegisterExecute {{ 107 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 108 { 109 Fault fault = NoFault; |
110 int64_t data; | 110 int64_t data M5_VAR_USED; |
111 %(op_decl)s; 112 %(op_rd)s; 113 114 VPEConf0Reg vpeConf0; 115 TCBindReg tcBindMT; 116 TCBindReg tcBind; 117 VPEControlReg vpeControl; 118 MVPConf0Reg mvpConf0; 119 120 getThrRegExValues(xc, vpeConf0, tcBindMT, 121 tcBind, vpeControl, mvpConf0); 122 123 if (isCoprocessorEnabled(xc, 0)) { 124 if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 125 data = -1; 126 } else if (vpeControl.targTC > mvpConf0.ptc) { 127 data = -1; 128 } else { | 111 %(op_decl)s; 112 %(op_rd)s; 113 114 VPEConf0Reg vpeConf0; 115 TCBindReg tcBindMT; 116 TCBindReg tcBind; 117 VPEControlReg vpeControl; 118 MVPConf0Reg mvpConf0; 119 120 getThrRegExValues(xc, vpeConf0, tcBindMT, 121 tcBind, vpeControl, mvpConf0); 122 123 if (isCoprocessorEnabled(xc, 0)) { 124 if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 125 data = -1; 126 } else if (vpeControl.targTC > mvpConf0.ptc) { 127 data = -1; 128 } else { |
129 int top_bit = 0; 130 int bottom_bit = 0; 131 132 if (MT_H == 1) { 133 top_bit = 63; 134 bottom_bit = 32; 135 } else { 136 top_bit = 31; 137 bottom_bit = 0; 138 } 139 | |
140 %(code)s; 141 } 142 } else { 143 fault = new CoprocessorUnusableFault(0); 144 } 145 146 if(fault == NoFault) 147 { --- 50 unchanged lines hidden (view full) --- 198 decode_block = BasicDecode.subst(iop) 199 exec_output = MTExecute.subst(iop) 200}}; 201 202def format MT_MFTR(code, *flags) {{ 203 flags += ('IsNonSpeculative', ) 204# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 205 | 129 %(code)s; 130 } 131 } else { 132 fault = new CoprocessorUnusableFault(0); 133 } 134 135 if(fault == NoFault) 136 { --- 50 unchanged lines hidden (view full) --- 187 decode_block = BasicDecode.subst(iop) 188 exec_output = MTExecute.subst(iop) 189}}; 190 191def format MT_MFTR(code, *flags) {{ 192 flags += ('IsNonSpeculative', ) 193# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 194 |
206 code += 'if (MT_H == 1) {\n' 207 code += 'data = bits(data, top_bit, bottom_bit);\n' 208 code += '}\n' 209 code += 'Rd = data;\n' | 195 code += ''' 196 if (MT_H) 197 data = bits(data, 63, 32); 198 Rd = data; 199 ''' |
210 211 iop = InstObjParams(name, Name, 'MTOp', code, flags) 212 header_output = BasicDeclare.subst(iop) 213 decoder_output = BasicConstructor.subst(iop) 214 decode_block = BasicDecode.subst(iop) 215 exec_output = ThreadRegisterExecute.subst(iop) 216}}; 217 218def format MT_MTTR(code, *flags) {{ 219 flags += ('IsNonSpeculative', ) 220# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 221 iop = InstObjParams(name, Name, 'MTOp', code, flags) 222 header_output = BasicDeclare.subst(iop) 223 decoder_output = BasicConstructor.subst(iop) 224 decode_block = BasicDecode.subst(iop) 225 exec_output = ThreadRegisterExecute.subst(iop) 226}}; | 200 201 iop = InstObjParams(name, Name, 'MTOp', code, flags) 202 header_output = BasicDeclare.subst(iop) 203 decoder_output = BasicConstructor.subst(iop) 204 decode_block = BasicDecode.subst(iop) 205 exec_output = ThreadRegisterExecute.subst(iop) 206}}; 207 208def format MT_MTTR(code, *flags) {{ 209 flags += ('IsNonSpeculative', ) 210# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 211 iop = InstObjParams(name, Name, 'MTOp', code, flags) 212 header_output = BasicDeclare.subst(iop) 213 decoder_output = BasicConstructor.subst(iop) 214 decode_block = BasicDecode.subst(iop) 215 exec_output = ThreadRegisterExecute.subst(iop) 216}}; |