mt.isa (5202:ff56fa8c2091) mt.isa (5222:bb733a878f85)
1// -*- mode:c++ -*-
2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
3// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
30
4
5// This software is part of the M5 simulator.
6
7// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
8// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9// TO THESE TERMS AND CONDITIONS.
10
11// Permission is granted to use, copy, create derivative works and
12// distribute this software and such derivative works for any purpose,
13// so long as (1) the copyright notice above, this grant of permission,
14// and the disclaimer below appear in all copies and derivative works
15// made, (2) the copyright notice above is augmented as appropriate to
16// reflect the addition of any new copyrightable work in a derivative
17// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
18// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
19// advertising or publicity pertaining to the use or distribution of
20// this software without specific, written prior authorization.
21
22// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
23// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
24// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
26// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
27// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
28// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
29// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
30// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
31// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
32// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
33// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
34
35//Authors: Korey L. Sewell
36
31////////////////////////////////////////////////////////////////////
32//
33// MT instructions
34//
35
36output header {{
37 /**
38 * Base class for MIPS MT ASE operations.

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67 };
68}};
69
70output decoder {{
71 std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
72 {
73 std::stringstream ss;
74
37////////////////////////////////////////////////////////////////////
38//
39// MT instructions
40//
41
42output header {{
43 /**
44 * Base class for MIPS MT ASE operations.

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73 };
74}};
75
76output decoder {{
77 std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
78 {
79 std::stringstream ss;
80
75 if (strcmp(mnemonic, "mttc0") == 0 || strcmp(mnemonic, "mftc0") == 0) {
81 if (mnemonic == "mttc0" || mnemonic == "mftc0") {
76 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
82 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
77 } else if (strcmp(mnemonic, "mftgpr") == 0) {
83 } else if (mnemonic == "mftgpr") {
78 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
79 } else {
80 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
81 }
82
83 return ss.str();
84 }
85}};

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91 tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
92 tc_bind = xc->readMiscReg(TCBind);
93 vpe_control = xc->readMiscReg(VPEControl);
94 mvp_conf0 = xc->readMiscReg(MVPConf0);
95 }
96
97 void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
98 {
84 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
85 } else {
86 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
87 }
88
89 return ss.str();
90 }
91}};

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97 tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
98 tc_bind = xc->readMiscReg(TCBind);
99 vpe_control = xc->readMiscReg(VPEControl);
100 mvp_conf0 = xc->readMiscReg(MVPConf0);
101 }
102
103 void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
104 {
99 config3 = xc->readMiscReg(Config3_MT);
105 config3 = xc->readMiscReg(Config3);
100 }
101}};
102
103def template ThreadRegisterExecute {{
104 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
105 {
106 Fault fault = NoFault;
107 int64_t data;

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130 } else {
131 top_bit = 31;
132 bottom_bit = 0;
133 }
134
135 %(code)s;
136 }
137 } else {
106 }
107}};
108
109def template ThreadRegisterExecute {{
110 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
111 {
112 Fault fault = NoFault;
113 int64_t data;

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136 } else {
137 top_bit = 31;
138 bottom_bit = 0;
139 }
140
141 %(code)s;
142 }
143 } else {
138 fault = new CoprocessorUnusableFault();
144 fault = new CoprocessorUnusableFault(0);
139 }
140
141 if(fault == NoFault)
142 {
143 %(op_wb)s;
144 }
145
146 return fault;

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160
161 if (isCoprocessorEnabled(xc, 0)) {
162 if (bits(config3, CFG3_MT) == 1) {
163 %(code)s;
164 } else {
165 fault = new ReservedInstructionFault();
166 }
167 } else {
145 }
146
147 if(fault == NoFault)
148 {
149 %(op_wb)s;
150 }
151
152 return fault;

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166
167 if (isCoprocessorEnabled(xc, 0)) {
168 if (bits(config3, CFG3_MT) == 1) {
169 %(code)s;
170 } else {
171 fault = new ReservedInstructionFault();
172 }
173 } else {
168 fault = new CoprocessorUnusableFault();
174 fault = new CoprocessorUnusableFault(0);
169 }
170
171 if(fault == NoFault)
172 {
173 %(op_wb)s;
174 }
175 return fault;
176 }

--- 45 unchanged lines hidden --- 		175 }
176
177 if(fault == NoFault)
178 {
179 %(op_wb)s;
180 }
181 return fault;
182 }

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