1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// MT instructions
34//
35
36output header {{
37 /**
38 * Base class for MIPS MT ASE operations.
39 */
40 class MTOp : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51
52 bool user_mode;
53 };
54
55 class MTUserModeOp : public MTOp
56 {
57 protected:
58
59 /// Constructor
60 MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
61 MTOp(mnem, _machInst, __opClass)
62 {
63 user_mode = true;
64 }
65
66 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67 };
68}};
69
70output decoder {{
71 std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
72 {
73 std::stringstream ss;
74
75 if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
76 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
77 } else if (strcmp(mnemonic,"mftgpr") == 0) {
78 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
79 } else {
80 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
81 }
82
83 return ss.str();
84 }
85}};
86
87output exec {{
88 void getThrRegExValues(%(CPU_exec_context)s *xc,
89 VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
90 TCBindReg &tc_bind, VPEControlReg &vpe_control,
91 MVPConf0Reg &mvp_conf0)
92 {
93 vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
94 tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
95 tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
96 vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
97 mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
98 }
99
100 void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3)
101 {
102 config3 = xc->readMiscReg(MISCREG_CONFIG3);
103 }
104}};
105
106def template ThreadRegisterExecute {{
107 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
108 {
109 Fault fault = NoFault;
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// MT instructions
34//
35
36output header {{
37 /**
38 * Base class for MIPS MT ASE operations.
39 */
40 class MTOp : public MipsStaticInst
41 {
42 protected:
43
44 /// Constructor
45 MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
46 MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
47 {
48 }
49
50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51
52 bool user_mode;
53 };
54
55 class MTUserModeOp : public MTOp
56 {
57 protected:
58
59 /// Constructor
60 MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
61 MTOp(mnem, _machInst, __opClass)
62 {
63 user_mode = true;
64 }
65
66 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67 };
68}};
69
70output decoder {{
71 std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
72 {
73 std::stringstream ss;
74
75 if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
76 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
77 } else if (strcmp(mnemonic,"mftgpr") == 0) {
78 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
79 } else {
80 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
81 }
82
83 return ss.str();
84 }
85}};
86
87output exec {{
88 void getThrRegExValues(%(CPU_exec_context)s *xc,
89 VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
90 TCBindReg &tc_bind, VPEControlReg &vpe_control,
91 MVPConf0Reg &mvp_conf0)
92 {
93 vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
94 tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
95 tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
96 vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
97 mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
98 }
99
100 void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3)
101 {
102 config3 = xc->readMiscReg(MISCREG_CONFIG3);
103 }
104}};
105
106def template ThreadRegisterExecute {{
107 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
108 {
109 Fault fault = NoFault;
|
140 %(code)s;
141 }
142 } else {
143 fault = new CoprocessorUnusableFault(0);
144 }
145
146 if(fault == NoFault)
147 {
148 %(op_wb)s;
149 }
150
151 return fault;
152 }
153}};
154
155def template MTExecute{{
156 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
157 {
158 Fault fault = NoFault;
159 %(op_decl)s;
160 %(op_rd)s;
161
162 Config3Reg config3;
163
164 getMTExValues(xc, config3);
165
166 if (isCoprocessorEnabled(xc, 0)) {
167 if (config3.mt == 1) {
168 %(code)s;
169 } else {
170 fault = new ReservedInstructionFault();
171 }
172 } else {
173 fault = new CoprocessorUnusableFault(0);
174 }
175
176 if(fault == NoFault)
177 {
178 %(op_wb)s;
179 }
180 return fault;
181 }
182}};
183
184// Primary format for integer operate instructions:
185def format MT_Control(code, *opt_flags) {{
186 inst_flags = ('IsNonSpeculative', )
187 op_type = 'MTOp'
188
189 for x in opt_flags:
190 if x == 'UserMode':
191 op_type = 'MTUserModeOp'
192 else:
193 inst_flags += (x, )
194
195 iop = InstObjParams(name, Name, op_type, code, inst_flags)
196 header_output = BasicDeclare.subst(iop)
197 decoder_output = BasicConstructor.subst(iop)
198 decode_block = BasicDecode.subst(iop)
199 exec_output = MTExecute.subst(iop)
200}};
201
202def format MT_MFTR(code, *flags) {{
203 flags += ('IsNonSpeculative', )
204# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
205
| 129 %(code)s;
130 }
131 } else {
132 fault = new CoprocessorUnusableFault(0);
133 }
134
135 if(fault == NoFault)
136 {
137 %(op_wb)s;
138 }
139
140 return fault;
141 }
142}};
143
144def template MTExecute{{
145 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
146 {
147 Fault fault = NoFault;
148 %(op_decl)s;
149 %(op_rd)s;
150
151 Config3Reg config3;
152
153 getMTExValues(xc, config3);
154
155 if (isCoprocessorEnabled(xc, 0)) {
156 if (config3.mt == 1) {
157 %(code)s;
158 } else {
159 fault = new ReservedInstructionFault();
160 }
161 } else {
162 fault = new CoprocessorUnusableFault(0);
163 }
164
165 if(fault == NoFault)
166 {
167 %(op_wb)s;
168 }
169 return fault;
170 }
171}};
172
173// Primary format for integer operate instructions:
174def format MT_Control(code, *opt_flags) {{
175 inst_flags = ('IsNonSpeculative', )
176 op_type = 'MTOp'
177
178 for x in opt_flags:
179 if x == 'UserMode':
180 op_type = 'MTUserModeOp'
181 else:
182 inst_flags += (x, )
183
184 iop = InstObjParams(name, Name, op_type, code, inst_flags)
185 header_output = BasicDeclare.subst(iop)
186 decoder_output = BasicConstructor.subst(iop)
187 decode_block = BasicDecode.subst(iop)
188 exec_output = MTExecute.subst(iop)
189}};
190
191def format MT_MFTR(code, *flags) {{
192 flags += ('IsNonSpeculative', )
193# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
194
|
210
211 iop = InstObjParams(name, Name, 'MTOp', code, flags)
212 header_output = BasicDeclare.subst(iop)
213 decoder_output = BasicConstructor.subst(iop)
214 decode_block = BasicDecode.subst(iop)
215 exec_output = ThreadRegisterExecute.subst(iop)
216}};
217
218def format MT_MTTR(code, *flags) {{
219 flags += ('IsNonSpeculative', )
220# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
221 iop = InstObjParams(name, Name, 'MTOp', code, flags)
222 header_output = BasicDeclare.subst(iop)
223 decoder_output = BasicConstructor.subst(iop)
224 decode_block = BasicDecode.subst(iop)
225 exec_output = ThreadRegisterExecute.subst(iop)
226}};
| 200
201 iop = InstObjParams(name, Name, 'MTOp', code, flags)
202 header_output = BasicDeclare.subst(iop)
203 decoder_output = BasicConstructor.subst(iop)
204 decode_block = BasicDecode.subst(iop)
205 exec_output = ThreadRegisterExecute.subst(iop)
206}};
207
208def format MT_MTTR(code, *flags) {{
209 flags += ('IsNonSpeculative', )
210# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
211 iop = InstObjParams(name, Name, 'MTOp', code, flags)
212 header_output = BasicDeclare.subst(iop)
213 decoder_output = BasicConstructor.subst(iop)
214 decode_block = BasicDecode.subst(iop)
215 exec_output = ThreadRegisterExecute.subst(iop)
216}};
|