| mem.isa (8564:f81bcb16fa1b) | mem.isa (8588:ef28ed90449d) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 529 unchanged lines hidden (view full) --- 538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 539 exec_template_base = 'Store') 540}}; 541 542 543def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 544 mem_flags = [], inst_flags = []) {{ 545 decl_code = ''' | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 529 unchanged lines hidden (view full) --- 538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 539 exec_template_base = 'Store') 540}}; 541 542 543def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 544 mem_flags = [], inst_flags = []) {{ 545 decl_code = ''' |
| 546 uint32_t mem_word = Mem.uw; | 546 uint32_t mem_word = Mem_uw; |
| 547 uint32_t unalign_addr = Rs + disp; 548 uint32_t byte_offset = unalign_addr & 3; 549 if (GuestByteOrder == BigEndianByteOrder) 550 byte_offset ^= 3; 551 ''' 552 553 memacc_code = decl_code + memacc_code 554 --- 42 unchanged lines hidden --- | 547 uint32_t unalign_addr = Rs + disp; 548 uint32_t byte_offset = unalign_addr & 3; 549 if (GuestByteOrder == BigEndianByteOrder) 550 byte_offset ^= 3; 551 ''' 552 553 memacc_code = decl_code + memacc_code 554 --- 42 unchanged lines hidden --- |