mem.isa (5736:426510e758ad) mem.isa (6207:c47f3e877a57)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 27 unchanged lines hidden (view full) ---

36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 27 unchanged lines hidden (view full) ---

36
37output header {{
38 /**
39 * Base class for general Mips memory-format instructions.
40 */
41 class Memory : public MipsStaticInst
42 {
43 protected:
44
45 /// Memory request flags. See mem_req_base.hh.
46 Request::Flags memAccessFlags;
44 /// Memory request flags. See mem_req_base.hh.
45 Request::Flags memAccessFlags;
47 /// Pointer to EAComp object.
48 const StaticInstPtr eaCompPtr;
49 /// Pointer to MemAcc object.
50 const StaticInstPtr memAccPtr;
51
52 /// Displacement for EA calculation (signed).
53 int32_t disp;
54
55 /// Constructor
46
47 /// Displacement for EA calculation (signed).
48 int32_t disp;
49
50 /// Constructor
56 Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
57 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
58 StaticInstPtr _memAccPtr = nullStaticInstPtr)
51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
59 : MipsStaticInst(mnem, _machInst, __opClass),
52 : MipsStaticInst(mnem, _machInst, __opClass),
60 eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
61 disp(sext<16>(OFFSET))
62 {
63 }
64
65 std::string
66 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
53 disp(sext<16>(OFFSET))
54 {
55 }
56
57 std::string
58 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67
68 public:
69
70 const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
71 const StaticInstPtr &memAccInst() const { return memAccPtr; }
72
73 Request::Flags memAccFlags() { return memAccessFlags; }
74 };
75
76 /**
77 * Base class for a few miscellaneous memory-format insts
78 * that don't interpret the disp field
79 */
80 class MemoryNoDisp : public Memory
81 {
82 protected:
83 /// Constructor
59 };
60
61 /**
62 * Base class for a few miscellaneous memory-format insts
63 * that don't interpret the disp field
64 */
65 class MemoryNoDisp : public Memory
66 {
67 protected:
68 /// Constructor
84 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
85 StaticInstPtr _eaCompPtr = nullStaticInstPtr,
86 StaticInstPtr _memAccPtr = nullStaticInstPtr)
87 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70 : Memory(mnem, _machInst, __opClass)
88 {
89 }
90
91 std::string
92 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
93 };
94}};
95

--- 48 unchanged lines hidden (view full) ---

144}};
145
146def template LoadStoreDeclare {{
147 /**
148 * Static instruction class for "%(mnemonic)s".
149 */
150 class %(class_name)s : public %(base_class)s
151 {
71 {
72 }
73
74 std::string
75 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76 };
77}};
78

--- 48 unchanged lines hidden (view full) ---

127}};
128
129def template LoadStoreDeclare {{
130 /**
131 * Static instruction class for "%(mnemonic)s".
132 */
133 class %(class_name)s : public %(base_class)s
134 {
152 protected:
153
154 /**
155 * "Fake" effective address computation class for "%(mnemonic)s".
156 */
157 class EAComp : public %(base_class)s
158 {
159 public:
160 /// Constructor
161 EAComp(ExtMachInst machInst);
162
163 %(BasicExecDeclare)s
164 };
165
166 /**
167 * "Fake" memory access instruction class for "%(mnemonic)s".
168 */
169 class MemAcc : public %(base_class)s
170 {
171 public:
172 /// Constructor
173 MemAcc(ExtMachInst machInst);
174
175 %(BasicExecDeclare)s
176 };
177
178 public:
179
180 /// Constructor.
181 %(class_name)s(ExtMachInst machInst);
182
183 %(BasicExecDeclare)s
184
135 public:
136
137 /// Constructor.
138 %(class_name)s(ExtMachInst machInst);
139
140 %(BasicExecDeclare)s
141
142 %(EACompDeclare)s
143
185 %(InitiateAccDeclare)s
186
187 %(CompleteAccDeclare)s
144 %(InitiateAccDeclare)s
145
146 %(CompleteAccDeclare)s
188
189 %(MemAccSizeDeclare)s
190 };
191}};
192
147 };
148}};
149
150def template EACompDeclare {{
151 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
152}};
193
194def template InitiateAccDeclare {{
195 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
196}};
197
198
199def template CompleteAccDeclare {{
200 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
201}};
202
153
154def template InitiateAccDeclare {{
155 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
156}};
157
158
159def template CompleteAccDeclare {{
160 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
203def template MemAccSizeDeclare {{
204 int memAccSize(%(CPU_exec_context)s *xc);
205}};
206
207
208def template MiscMemAccSize {{
209 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
210 {
211 panic("Misc instruction does not support split access method!");
212 return 0;
213 }
214}};
215
216def template EACompConstructor {{
217 /** TODO: change op_class to AddrGenOp or something (requires
218 * creating new member of OpClass enum in op_class.hh, updating
219 * config files, etc.). */
220 inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
221 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
222 {
223 %(constructor)s;
224 }
225}};
226
227
228def template MemAccConstructor {{
229 inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
230 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
231 {
232 %(constructor)s;
233 }
234}};
235
236
237def template LoadStoreConstructor {{
238 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
163def template LoadStoreConstructor {{
164 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
239 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
240 new EAComp(machInst), new MemAcc(machInst))
165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
241 {
242 %(constructor)s;
243 }
244}};
245
246
247def template EACompExecute {{
248 Fault
166 {
167 %(constructor)s;
168 }
169}};
170
171
172def template EACompExecute {{
173 Fault
249 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
174 %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
250 Trace::InstRecord *traceData) const
251 {
252 Addr EA;
253 Fault fault = NoFault;
254
255 if (this->isFloating()) {
256 %(fp_enable_check)s;
257

--- 9 unchanged lines hidden (view full) ---

267 if (fault == NoFault) {
268 xc->setEA(EA);
269 }
270
271 return fault;
272 }
273}};
274
175 Trace::InstRecord *traceData) const
176 {
177 Addr EA;
178 Fault fault = NoFault;
179
180 if (this->isFloating()) {
181 %(fp_enable_check)s;
182

--- 9 unchanged lines hidden (view full) ---

192 if (fault == NoFault) {
193 xc->setEA(EA);
194 }
195
196 return fault;
197 }
198}};
199
275def template LoadStoreFPEACompExecute {{
276 Fault
277 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
278 Trace::InstRecord *traceData) const
279 {
280 Addr EA;
281 Fault fault = NoFault;
282
283 %(fp_enable_check)s;
284 if(fault != NoFault)
285 return fault;
286 %(op_decl)s;
287 %(op_rd)s;
288 %(ea_code)s;
289
290 // NOTE: Trace Data is written using execute or completeAcc templates
291 if (fault == NoFault) {
292 xc->setEA(EA);
293 }
294
295 return fault;
296 }
297}};
298
299
300def template LoadMemAccExecute {{
301 Fault
302 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
303 Trace::InstRecord *traceData) const
304 {
305 Addr EA;
306
307 Fault fault = NoFault;
308
309 if (this->isFloating()) {
310 %(fp_enable_check)s;
311
312 if(fault != NoFault)
313 return fault;
314 }
315
316 %(op_decl)s;
317 %(op_rd)s;
318
319 EA = xc->getEA();
320
321 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
322
323 %(memacc_code)s;
324
325 // NOTE: Write back data using execute or completeAcc templates
326
327 return fault;
328 }
329}};
330
331
332def template LoadExecute {{
333 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
334 Trace::InstRecord *traceData) const
335 {
336 Addr EA;
337 Fault fault = NoFault;
338
339 if (this->isFloating()) {

--- 73 unchanged lines hidden (view full) ---

413 if (fault == NoFault) {
414 %(op_wb)s;
415 }
416
417 return fault;
418 }
419}};
420
200def template LoadExecute {{
201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
202 Trace::InstRecord *traceData) const
203 {
204 Addr EA;
205 Fault fault = NoFault;
206
207 if (this->isFloating()) {

--- 73 unchanged lines hidden (view full) ---

281 if (fault == NoFault) {
282 %(op_wb)s;
283 }
284
285 return fault;
286 }
287}};
288
421
422def template LoadStoreMemAccSize {{
423 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
424 {
425 // Return the memory access size in bytes
426 return (%(mem_acc_size)d / 8);
427 }
428}};
429
430def template StoreMemAccExecute {{
431 Fault
432 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
433 Trace::InstRecord *traceData) const
434 {
435 Addr EA;
436 Fault fault = NoFault;
437
438 %(fp_enable_check)s;
439 %(op_decl)s;
440 %(op_rd)s;
441
442 EA = xc->getEA();
443
444 if (fault == NoFault) {
445 %(memacc_code)s;
446 }
447
448 if (fault == NoFault) {
449 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
450 memAccessFlags, NULL);
451 // @NOTE: Need to Call Complete Access to Set Trace Data
452 //if (traceData) { traceData->setData(Mem); }
453 }
454
455 return fault;
456 }
457}};
458
459def template StoreCondMemAccExecute {{
460 Fault
461 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
462 Trace::InstRecord *traceData) const
463 {
464 Addr EA;
465 Fault fault = NoFault;
466 uint64_t write_result = 0;
467
468 %(fp_enable_check)s;
469 %(op_decl)s;
470 %(op_rd)s;
471 EA = xc->getEA();
472
473 if (fault == NoFault) {
474 %(memacc_code)s;
475 }
476
477 if (fault == NoFault) {
478 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
479 memAccessFlags, &write_result);
480 if (traceData) { traceData->setData(Mem); }
481 }
482
483 if (fault == NoFault) {
484 %(postacc_code)s;
485 }
486
487 if (fault == NoFault) {
488 %(op_wb)s;
489 }
490
491 return fault;
492 }
493}};
494
495def template StoreExecute {{
496 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
497 Trace::InstRecord *traceData) const
498 {
499 Addr EA;
500 Fault fault = NoFault;
501
502 %(fp_enable_check)s;

--- 189 unchanged lines hidden (view full) ---

692 if (fault == NoFault) {
693 %(op_wb)s;
694 }
695
696 return fault;
697 }
698}};
699
289def template StoreExecute {{
290 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
291 Trace::InstRecord *traceData) const
292 {
293 Addr EA;
294 Fault fault = NoFault;
295
296 %(fp_enable_check)s;

--- 189 unchanged lines hidden (view full) ---

486 if (fault == NoFault) {
487 %(op_wb)s;
488 }
489
490 return fault;
491 }
492}};
493
700
701def template MiscMemAccExecute {{
702 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
703 Trace::InstRecord *traceData) const
704 {
705 Addr EA;
706 Fault fault = NoFault;
707
708 %(fp_enable_check)s;
709 %(op_decl)s;
710 %(op_rd)s;
711 EA = xc->getEA();
712
713 if (fault == NoFault) {
714 %(memacc_code)s;
715 }
716
717 return NoFault;
718 }
719}};
720
721def template MiscExecute {{
722 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
723 Trace::InstRecord *traceData) const
724 {
725 Addr EA;
726 Fault fault = NoFault;
727
728 %(fp_enable_check)s;

--- 25 unchanged lines hidden (view full) ---

754 Trace::InstRecord *traceData) const
755 {
756 panic("Misc instruction does not support split access method!");
757
758 return NoFault;
759 }
760}};
761
494def template MiscExecute {{
495 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
496 Trace::InstRecord *traceData) const
497 {
498 Addr EA;
499 Fault fault = NoFault;
500
501 %(fp_enable_check)s;

--- 25 unchanged lines hidden (view full) ---

527 Trace::InstRecord *traceData) const
528 {
529 panic("Misc instruction does not support split access method!");
530
531 return NoFault;
532 }
533}};
534
762
763def template MiscMemAccSize {{
764 int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
765 {
766 panic("Misc instruction does not support split access method!");
767 return 0;
768 }
769}};
770
771def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
772 mem_flags = [], inst_flags = []) {{
773 (header_output, decoder_output, decode_block, exec_output) = \
774 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
775 decode_template = ImmNopCheckDecode,
776 exec_template_base = 'Load')
777}};
778

--- 97 unchanged lines hidden --- 		535def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
536 mem_flags = [], inst_flags = []) {{
537 (header_output, decoder_output, decode_block, exec_output) = \
538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
539 decode_template = ImmNopCheckDecode,
540 exec_template_base = 'Load')
541}};
542

--- 97 unchanged lines hidden ---