mem.isa (3349:fec4a86fa212) mem.isa (3953:300d526414e6)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 152 unchanged lines hidden (view full) ---

161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 152 unchanged lines hidden (view full) ---

161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
169def template LoadStoreConstructor {{
169def template EACompConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
175 {
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
175 {
176 %(ea_constructor)s;
176 %(constructor)s;
177 }
177 }
178}};
178
179
180
181def template MemAccConstructor {{
179 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
180 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
181 {
182 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
183 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
184 {
182 %(memacc_constructor)s;
185 %(constructor)s;
183 }
186 }
187}};
184
188
189
190def template LoadStoreConstructor {{
185 inline %(class_name)s::%(class_name)s(MachInst machInst)
186 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
187 new EAComp(machInst), new MemAcc(machInst))
188 {
189 %(constructor)s;
190 }
191}};
192

--- 4 unchanged lines hidden (view full) ---

197 Trace::InstRecord *traceData) const
198 {
199 Addr EA;
200 Fault fault = NoFault;
201
202 %(fp_enable_check)s;
203 %(op_decl)s;
204 %(op_rd)s;
191 inline %(class_name)s::%(class_name)s(MachInst machInst)
192 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
193 new EAComp(machInst), new MemAcc(machInst))
194 {
195 %(constructor)s;
196 }
197}};
198

--- 4 unchanged lines hidden (view full) ---

203 Trace::InstRecord *traceData) const
204 {
205 Addr EA;
206 Fault fault = NoFault;
207
208 %(fp_enable_check)s;
209 %(op_decl)s;
210 %(op_rd)s;
205 %(code)s;
211 %(ea_code)s;
206
207 if (fault == NoFault) {
208 %(op_wb)s;
209 xc->setEA(EA);
210 }
211
212 return fault;
213 }

--- 9 unchanged lines hidden (view full) ---

223
224 %(fp_enable_check)s;
225 %(op_decl)s;
226 %(op_rd)s;
227 EA = xc->getEA();
228
229 if (fault == NoFault) {
230 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
212
213 if (fault == NoFault) {
214 %(op_wb)s;
215 xc->setEA(EA);
216 }
217
218 return fault;
219 }

--- 9 unchanged lines hidden (view full) ---

229
230 %(fp_enable_check)s;
231 %(op_decl)s;
232 %(op_rd)s;
233 EA = xc->getEA();
234
235 if (fault == NoFault) {
236 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
231 %(code)s;
237 %(memacc_code)s;
232 }
233
234 if (fault == NoFault) {
235 %(op_wb)s;
236 }
237
238 return fault;
239 }

--- 82 unchanged lines hidden (view full) ---

322 uint64_t write_result = 0;
323
324 %(fp_enable_check)s;
325 %(op_decl)s;
326 %(op_rd)s;
327 EA = xc->getEA();
328
329 if (fault == NoFault) {
238 }
239
240 if (fault == NoFault) {
241 %(op_wb)s;
242 }
243
244 return fault;
245 }

--- 82 unchanged lines hidden (view full) ---

328 uint64_t write_result = 0;
329
330 %(fp_enable_check)s;
331 %(op_decl)s;
332 %(op_rd)s;
333 EA = xc->getEA();
334
335 if (fault == NoFault) {
330 %(code)s;
336 %(memacc_code)s;
331 }
332
333 if (fault == NoFault) {
334 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
335 memAccessFlags, &write_result);
336 if (traceData) { traceData->setData(Mem); }
337 }
338

--- 127 unchanged lines hidden (view full) ---

466 Fault fault = NoFault;
467
468 %(fp_enable_check)s;
469 %(op_decl)s;
470 %(op_rd)s;
471 EA = xc->getEA();
472
473 if (fault == NoFault) {
337 }
338
339 if (fault == NoFault) {
340 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
341 memAccessFlags, &write_result);
342 if (traceData) { traceData->setData(Mem); }
343 }
344

--- 127 unchanged lines hidden (view full) ---

472 Fault fault = NoFault;
473
474 %(fp_enable_check)s;
475 %(op_decl)s;
476 %(op_rd)s;
477 EA = xc->getEA();
478
479 if (fault == NoFault) {
474 %(code)s;
480 %(memacc_code)s;
475 }
476
477 return NoFault;
478 }
479}};
480
481def template MiscExecute {{
482 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,

--- 122 unchanged lines hidden --- 		481 }
482
483 return NoFault;
484 }
485}};
486
487def template MiscExecute {{
488 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,

--- 122 unchanged lines hidden ---