mem.isa (2935:d1223a6c9156) mem.isa (3349:fec4a86fa212)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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157
158
159def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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157
158
159def template InitiateAccDeclare {{
160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
169def template LoadStoreConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)

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283 }
284
285 return fault;
286 }
287}};
288
289
290def template LoadCompleteAcc {{
166}};
167
168
169def template LoadStoreConstructor {{
170 /** TODO: change op_class to AddrGenOp or something (requires
171 * creating new member of OpClass enum in op_class.hh, updating
172 * config files, etc.). */
173 inline %(class_name)s::EAComp::EAComp(MachInst machInst)

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283 }
284
285 return fault;
286 }
287}};
288
289
290def template LoadCompleteAcc {{
291 Fault %(class_name)s::completeAcc(Packet *pkt,
291 Fault %(class_name)s::completeAcc(PacketPtr pkt,
292 %(CPU_exec_context)s *xc,
293 Trace::InstRecord *traceData) const
294 {
295 Fault fault = NoFault;
296
297 %(fp_enable_check)s;
298 %(op_decl)s;
299

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407 }
408
409 return fault;
410 }
411}};
412
413
414def template StoreCompleteAcc {{
292 %(CPU_exec_context)s *xc,
293 Trace::InstRecord *traceData) const
294 {
295 Fault fault = NoFault;
296
297 %(fp_enable_check)s;
298 %(op_decl)s;
299

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407 }
408
409 return fault;
410 }
411}};
412
413
414def template StoreCompleteAcc {{
415 Fault %(class_name)s::completeAcc(Packet *pkt,
415 Fault %(class_name)s::completeAcc(PacketPtr pkt,
416 %(CPU_exec_context)s *xc,
417 Trace::InstRecord *traceData) const
418 {
419 Fault fault = NoFault;
420
421 %(fp_enable_check)s;
422 %(op_dest_decl)s;
423

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429 %(op_wb)s;
430 }
431
432 return fault;
433 }
434}};
435
436def template StoreCondCompleteAcc {{
416 %(CPU_exec_context)s *xc,
417 Trace::InstRecord *traceData) const
418 {
419 Fault fault = NoFault;
420
421 %(fp_enable_check)s;
422 %(op_dest_decl)s;
423

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429 %(op_wb)s;
430 }
431
432 return fault;
433 }
434}};
435
436def template StoreCondCompleteAcc {{
437 Fault %(class_name)s::completeAcc(Packet *pkt,
437 Fault %(class_name)s::completeAcc(PacketPtr pkt,
438 %(CPU_exec_context)s *xc,
439 Trace::InstRecord *traceData) const
440 {
441 Fault fault = NoFault;
442
443 %(fp_enable_check)s;
444 %(op_dest_decl)s;
445

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504 {
505 panic("Misc instruction does not support split access method!");
506 return NoFault;
507 }
508}};
509
510
511def template MiscCompleteAcc {{
438 %(CPU_exec_context)s *xc,
439 Trace::InstRecord *traceData) const
440 {
441 Fault fault = NoFault;
442
443 %(fp_enable_check)s;
444 %(op_dest_decl)s;
445

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504 {
505 panic("Misc instruction does not support split access method!");
506 return NoFault;
507 }
508}};
509
510
511def template MiscCompleteAcc {{
512 Fault %(class_name)s::completeAcc(Packet *pkt,
512 Fault %(class_name)s::completeAcc(PacketPtr pkt,
513 %(CPU_exec_context)s *xc,
514 Trace::InstRecord *traceData) const
515 {
516 panic("Misc instruction does not support split access method!");
517
518 return NoFault;
519 }
520}};

--- 84 unchanged lines hidden --- 		513 %(CPU_exec_context)s *xc,
514 Trace::InstRecord *traceData) const
515 {
516 panic("Misc instruction does not support split access method!");
517
518 return NoFault;
519 }
520}};

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