mem.isa (2754:e3d023bc752c) | mem.isa (2935:d1223a6c9156) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 12 unchanged lines hidden (view full) --- 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// |
29// Authors: Gabe Black | 29// Authors: Steve Reinhardt |
30// Korey Sewell 31 32//////////////////////////////////////////////////////////////////// 33// 34// Memory-format instructions 35// 36 37output header {{ --- 119 unchanged lines hidden (view full) --- 157 158 159def template InitiateAccDeclare {{ 160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163 164def template CompleteAccDeclare {{ | 30// Korey Sewell 31 32//////////////////////////////////////////////////////////////////// 33// 34// Memory-format instructions 35// 36 37output header {{ --- 119 unchanged lines hidden (view full) --- 157 158 159def template InitiateAccDeclare {{ 160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163 164def template CompleteAccDeclare {{ |
165 Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; | 165 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; |
166}}; 167 168 169def template LoadStoreConstructor {{ 170 /** TODO: change op_class to AddrGenOp or something (requires 171 * creating new member of OpClass enum in op_class.hh, updating 172 * config files, etc.). */ 173 inline %(class_name)s::EAComp::EAComp(MachInst machInst) --- 109 unchanged lines hidden (view full) --- 283 } 284 285 return fault; 286 } 287}}; 288 289 290def template LoadCompleteAcc {{ | 166}}; 167 168 169def template LoadStoreConstructor {{ 170 /** TODO: change op_class to AddrGenOp or something (requires 171 * creating new member of OpClass enum in op_class.hh, updating 172 * config files, etc.). */ 173 inline %(class_name)s::EAComp::EAComp(MachInst machInst) --- 109 unchanged lines hidden (view full) --- 283 } 284 285 return fault; 286 } 287}}; 288 289 290def template LoadCompleteAcc {{ |
291 Fault %(class_name)s::completeAcc(uint8_t *data, | 291 Fault %(class_name)s::completeAcc(Packet *pkt, |
292 %(CPU_exec_context)s *xc, 293 Trace::InstRecord *traceData) const 294 { 295 Fault fault = NoFault; 296 297 %(fp_enable_check)s; 298 %(op_decl)s; 299 | 292 %(CPU_exec_context)s *xc, 293 Trace::InstRecord *traceData) const 294 { 295 Fault fault = NoFault; 296 297 %(fp_enable_check)s; 298 %(op_decl)s; 299 |
300 memcpy(&Mem, data, sizeof(Mem)); | 300 Mem = pkt->get<typeof(Mem)>(); |
301 302 if (fault == NoFault) { 303 %(memacc_code)s; 304 } 305 306 if (fault == NoFault) { 307 %(op_wb)s; 308 } --- 76 unchanged lines hidden (view full) --- 385}}; 386 387def template StoreInitiateAcc {{ 388 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 389 Trace::InstRecord *traceData) const 390 { 391 Addr EA; 392 Fault fault = NoFault; | 301 302 if (fault == NoFault) { 303 %(memacc_code)s; 304 } 305 306 if (fault == NoFault) { 307 %(op_wb)s; 308 } --- 76 unchanged lines hidden (view full) --- 385}}; 386 387def template StoreInitiateAcc {{ 388 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 389 Trace::InstRecord *traceData) const 390 { 391 Addr EA; 392 Fault fault = NoFault; |
393 uint64_t write_result = 0; | |
394 395 %(fp_enable_check)s; 396 %(op_decl)s; 397 %(op_rd)s; 398 %(ea_code)s; 399 400 if (fault == NoFault) { 401 %(memacc_code)s; 402 } 403 404 if (fault == NoFault) { 405 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, | 393 394 %(fp_enable_check)s; 395 %(op_decl)s; 396 %(op_rd)s; 397 %(ea_code)s; 398 399 if (fault == NoFault) { 400 %(memacc_code)s; 401 } 402 403 if (fault == NoFault) { 404 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, |
406 memAccessFlags, &write_result); | 405 memAccessFlags, NULL); |
407 if (traceData) { traceData->setData(Mem); } 408 } 409 410 return fault; 411 } 412}}; 413 414 415def template StoreCompleteAcc {{ | 406 if (traceData) { traceData->setData(Mem); } 407 } 408 409 return fault; 410 } 411}}; 412 413 414def template StoreCompleteAcc {{ |
416 Fault %(class_name)s::completeAcc(uint8_t *data, | 415 Fault %(class_name)s::completeAcc(Packet *pkt, |
417 %(CPU_exec_context)s *xc, 418 Trace::InstRecord *traceData) const 419 { 420 Fault fault = NoFault; | 416 %(CPU_exec_context)s *xc, 417 Trace::InstRecord *traceData) const 418 { 419 Fault fault = NoFault; |
421 uint64_t write_result = 0; | |
422 423 %(fp_enable_check)s; 424 %(op_dest_decl)s; 425 | 420 421 %(fp_enable_check)s; 422 %(op_dest_decl)s; 423 |
426 memcpy(&write_result, data, sizeof(write_result)); | 424 if (fault == NoFault) { 425 %(postacc_code)s; 426 } |
427 428 if (fault == NoFault) { | 427 428 if (fault == NoFault) { |
429 %(op_wb)s; 430 } 431 432 return fault; 433 } 434}}; 435 436def template StoreCondCompleteAcc {{ 437 Fault %(class_name)s::completeAcc(Packet *pkt, 438 %(CPU_exec_context)s *xc, 439 Trace::InstRecord *traceData) const 440 { 441 Fault fault = NoFault; 442 443 %(fp_enable_check)s; 444 %(op_dest_decl)s; 445 446 uint64_t write_result = pkt->req->getScResult(); 447 448 if (fault == NoFault) { |
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429 %(postacc_code)s; 430 } 431 432 if (fault == NoFault) { 433 %(op_wb)s; 434 } 435 436 return fault; --- 47 unchanged lines hidden (view full) --- 484 { 485 panic("Misc instruction does not support split access method!"); 486 return NoFault; 487 } 488}}; 489 490 491def template MiscCompleteAcc {{ | 449 %(postacc_code)s; 450 } 451 452 if (fault == NoFault) { 453 %(op_wb)s; 454 } 455 456 return fault; --- 47 unchanged lines hidden (view full) --- 504 { 505 panic("Misc instruction does not support split access method!"); 506 return NoFault; 507 } 508}}; 509 510 511def template MiscCompleteAcc {{ |
492 Fault %(class_name)s::completeAcc(uint8_t *data, | 512 Fault %(class_name)s::completeAcc(Packet *pkt, |
493 %(CPU_exec_context)s *xc, 494 Trace::InstRecord *traceData) const 495 { 496 panic("Misc instruction does not support split access method!"); 497 498 return NoFault; 499 } 500}}; --- 74 unchanged lines hidden (view full) --- 575 576}}; 577 578def format StoreCond(memacc_code, postacc_code, 579 ea_code = {{ EA = Rs + disp; }}, 580 mem_flags = [], inst_flags = []) {{ 581 (header_output, decoder_output, decode_block, exec_output) = \ 582 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, | 513 %(CPU_exec_context)s *xc, 514 Trace::InstRecord *traceData) const 515 { 516 panic("Misc instruction does not support split access method!"); 517 518 return NoFault; 519 } 520}}; --- 74 unchanged lines hidden (view full) --- 595 596}}; 597 598def format StoreCond(memacc_code, postacc_code, 599 ea_code = {{ EA = Rs + disp; }}, 600 mem_flags = [], inst_flags = []) {{ 601 (header_output, decoder_output, decode_block, exec_output) = \ 602 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |
583 postacc_code, exec_template_base = 'Store') | 603 postacc_code, exec_template_base = 'StoreCond') |
584}}; | 604}}; |