1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 76 unchanged lines hidden (view full) --- 85 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 86 { 87 return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 88 flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 89 } 90 91}}; 92 |
93def template LoadStoreDeclare {{ 94 /** 95 * Static instruction class for "%(mnemonic)s". 96 */ 97 class %(class_name)s : public %(base_class)s 98 { 99 protected: 100 --- 311 unchanged lines hidden (view full) --- 412 if (fault == NoFault) { 413 %(op_wb)s; 414 } 415 416 return fault; 417 } 418}}; 419 |
420 421def template MiscMemAccExecute {{ 422 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 423 Trace::InstRecord *traceData) const 424 { 425 Addr EA; 426 Fault fault = NoFault; 427 428 %(fp_enable_check)s; 429 %(op_decl)s; 430 %(op_rd)s; 431 EA = xc->getEA(); 432 433 if (fault == NoFault) { 434 %(code)s; 435 } 436 437 return NoFault; 438 } 439}}; 440 441def template MiscExecute {{ 442 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 443 Trace::InstRecord *traceData) const 444 { 445 Addr EA; 446 Fault fault = NoFault; 447 448 %(fp_enable_check)s; 449 %(op_decl)s; 450 %(op_rd)s; 451 %(ea_code)s; 452 453 if (fault == NoFault) { 454 %(memacc_code)s; 455 } 456 457 return NoFault; 458 } 459}}; 460 461def template MiscInitiateAcc {{ 462 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 463 Trace::InstRecord *traceData) const 464 { 465 panic("Misc instruction does not support split access method!"); 466 return NoFault; 467 } 468}}; 469 470 471def template MiscCompleteAcc {{ 472 Fault %(class_name)s::completeAcc(uint8_t *data, 473 %(CPU_exec_context)s *xc, 474 Trace::InstRecord *traceData) const 475 { 476 panic("Misc instruction does not support split access method!"); 477 478 return NoFault; 479 } 480}}; 481 |
482// load instructions use Rt as dest, so check for |
483// Rt == 0 to detect nops |
484def template LoadNopCheckDecode {{ 485 { 486 MipsStaticInst *i = new %(class_name)s(machInst); 487 if (RT == 0) { 488 i = makeNop(i); 489 } 490 return i; 491 } 492}}; 493 494def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 495 mem_flags = [], inst_flags = []) {{ 496 (header_output, decoder_output, decode_block, exec_output) = \ 497 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 498 decode_template = LoadNopCheckDecode, 499 exec_template_base = 'Load') 500}}; 501 |
502def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 503 mem_flags = [], inst_flags = []) {{ 504 (header_output, decoder_output, decode_block, exec_output) = \ 505 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 506 exec_template_base = 'Store') 507}}; 508 |
509def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, |
510 mem_flags = [], inst_flags = []) {{ 511 (header_output, decoder_output, decode_block, exec_output) = \ 512 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |
513 decode_template = LoadNopCheckDecode, |
514 exec_template_base = 'Load') 515}}; 516 |
517def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 518 mem_flags = [], inst_flags = []) {{ 519 (header_output, decoder_output, decode_block, exec_output) = \ 520 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 521 exec_template_base = 'Store') 522}}; |
523 |
524def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, |
525 mem_flags = [], inst_flags = []) {{ |
526 decl_code = 'uint32_t mem_word = Mem.uw;\n' 527 decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 528 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 529 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 530 decl_code += '\tbyte_offset ^= 3;\n' 531 decl_code += '#endif\n' 532 533 memacc_code = decl_code + memacc_code 534 |
535 (header_output, decoder_output, decode_block, exec_output) = \ 536 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |
537 decode_template = LoadNopCheckDecode, 538 exec_template_base = 'Load') 539}}; 540 541def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 542 mem_flags = [], inst_flags = []) {{ 543 decl_code = 'uint32_t mem_word = 0;\n' 544 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 545 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 546 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 547 decl_code += '\tbyte_offset ^= 3;\n' 548 decl_code += '#endif\n' 549 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 550 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 551 552 (header_output, decoder_output, decode_block, exec_output) = \ 553 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 554 decode_template = LoadNopCheckDecode, |
555 exec_template_base = 'Store') 556}}; 557 |
558def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 559 mem_flags = [], pf_flags = [], inst_flags = []) {{ 560 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 561 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 562 'IsDataPrefetch', 'MemReadOp'] |
563 |
564 (header_output, decoder_output, decode_block, exec_output) = \ 565 LoadStoreBase(name, Name, ea_code, 566 'xc->prefetch(EA, memAccessFlags);', 567 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 568 569}}; 570 571def format StoreCond(memacc_code, postacc_code, 572 ea_code = {{ EA = Rs + disp; }}, |
573 mem_flags = [], inst_flags = []) {{ 574 (header_output, decoder_output, decode_block, exec_output) = \ 575 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 576 postacc_code, exec_template_base = 'Store') 577}}; |